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參數資料
| 型號： | L9310 |
| 英文描述： | Line Interface and Line Access Circuit Full-Feature SLIC,Ringing Relay,and Test Access Device |
| 中文描述： | 線路接口和線路接入電路全功能用戶接口，振鈴繼電器，測試接入設備 |
| 文件頁數： | 27/60頁 |
| 文件大?。?/td> | 1053K |
| 代理商： | L9310 |
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Data Sheet
July 2001
Full-Feature SLIC, Ringing Relay, and Test Access Device
L9310 Line Interface and Line Access Circuit
Agere Systems Inc.
27
Electrical Characteristics
(continued)
Logic Inputs and Outputs, V
DD
= 5.0 V
Table 13. Logic Inputs and Outputs
Timing Requirements
Table 14. Timing Requirements
Data control is via a parallel latched data control scheme. Data latches are edge-level sensitive. Data is latched in
when the LATCH control input goes low. Data must be set up t
SU
ns before LATCH goes low and held t
HL
ns after
LATCH goes high. While LATCH is low, the user should not change the data control inputs at B0, B1, B2, and B3.
The data control inputs at B0, B1, B2, and B3 may only be changed when LATCH is high. NSTAT supervision out-
put is not controlled by the LATCH control input.
12-3526(F)
Figure 4. Timing Requirements
Parameter
Symbol
V
IL
V
IH
Min
Typ
Max
Unit
Input Voltages:
Low Level
High Level
Input Current:
Low Level (V
DD
= 5.25 V, V
I
= 0.4 V)
High Level (V
DD
= 5.25 V, V
I
= 2.4 V)
Output Voltages (CMOS):
Low Level (V
DD
= 4.75 V, I
OL
= 180
μ
A)
High Level (V
DD
= 4.75 V, I
OH
= –20
μ
A)
–0.5
2.0
0.4
2.4
0.7
V
DD
V
V
I
IL
I
IH
—
—
—
—
±50
±50
μ
A
μ
A
V
OL
V
OH
0
2.4
0.2
—
0.4
V
CC
V
V
Parameter
Symbol
t
SU
t
HL
Min
200
50
Typ
—
—
Max
—
—
Unit
ns
ns
Minimum Setup Time from B0, B1, B2, B3 to LATCH
Minimum Hold Time from LATCH to B0, B1, B2, B3
t
SU
t
HL
LATCH
B0, B1,
B2, B3
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