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參數(shù)資料
| 型號(hào)： | L9949TR |
| 廠商： | STMICROELECTRONICS |
| 元件分類： | 運(yùn)動(dòng)控制電子 |
| 英文描述： | BRUSH DC MOTOR CONTROLLER, 10 A, PDSO20 |
| 封裝： | POWER, SO-20 |
| 文件頁數(shù)： | 8/22頁 |
| 文件大小： | 418K |
| 代理商： | L9949TR |
L9949
16/20
Figure 8. SPI-Interface - Transfer Timing Diagram
IDOLK
Tristate Leakage Current
VCSN =VCC, 0 V < VDO <VCC
-10
10
A
CDO
Tristate Input Capacitance
VCSN =VCC,
0 V<VCC <5.5 V
10
15
pF
DO timing (see Figg. 10 & 11)
tr DO
DO Rise Time
CL =100 pF, Iload = -1mA
50
100
ns
tf DO
Data Out Fall Time
CL =100 pF, Iload = 1mA
50
100
ns
ten DO tri L DO Enable Time
from tristate to low level
CL =100 pF, Iload = 1mA
pull-up load to VCC
80
250
ns
ten DO L tri DO Disable Time
from low level totristate
CL =100 pF, Iload = 4mA
pull-up load to VCC
200
400
ns
ten DO tri H DO Enable Time
from tristate to high level
CL =100 pF, Iload = -1mA
pull-down load to GND
80
250
ns
ten DOH tri DO Disable Time
from high level totristate
CL =100 pF, Iload = -4mA
ppull-down load to GND
200
400
ns
td DO
DO Delay Time
VDO < 0.3 VCC, VDO > 0.7 VCC,
CL =100 pF
50
250
ns
(1)
Value of input capacity is not measured in production test. Parameter guarenteed by design.
(2)
DI timing parameters tested in production by a passed/failed test:
Tj=-40°C/+25°C: SPI communication @2MHz
Tj=+125°C:
SPI communication @1.25MHz
SPI INTERFACE ELECTRICAL CHARACTERISTCS (continued)
VS =8to 16 V, VCC = 4.5 to 5.5 V, Tj = -40 to 150 °C, unless otherwise specified. The voltages are refered to
GND and currents are assumed positive, when the current flows into the pin
.
Symbol
Parameter
Test Condition
Min.
Typ.
Max.
Unit
0
1
0
1
time
CSN high to low: DO enabled
actual data
DI: data will be accepted on the rising edge of CLK signal
new data
CSN
CLK
DI
DO
e.g.OUT1
DO: data will change on the falling edge of CLK signal
status information
fault bit
CSN low to high: actual data is
transfered to output power switches
old data
12
3
4
5
6
78
9
10 11
012
13 14 15
1
0
actual
l
data
1
2
3
456
78
9
10 11
012
13 14 15
1
2
3
456
78
9
10 11
012
13 14 15
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