
Deflection Block - Input Signals and Test Conditions
For each of the test items, set up the following conditions unless otherwise specified.
1. VIF and SIF blocks: No signal
2. Luminance (Y) input and chrominance (C) input: No signal
3. Sync input: Horizontal/vertical composite sync signal (DC offset: 3.8 V, 40 IRE. Other timing and other parameters
must conform to the FCC broadcast standards.)
Caution: There must be no burst or chrominance signal under the pedestal level.
4. Bus control conditions: All conditions set to their initial values, unless otherwise specified.
5. The delay time from the rise of the horizontal output (the pin 26 output) to the rise of the F.B.P IN (pin 27 input)
must be 9 s.
6. The pin 18 (the vertical size correction circuit input pin) voltage must be VCC (7.6 V).
7. Pin 28 (the x-ray protection circuit input pin) must be connected to ground.
Notes:
Perform the following operations if the horizontal output pulse signal was stopped.
1. Set the bus on/off bit to off (0) temporarily, and then set it to on (1) again.
(If the x-ray protection circuit and/or the PON-RES circuit operate, an IC internal latch circuit will be set. The on/off
bit must be set to off (0) to reset that latch circuit, even if the horizontal output signal is not output. Since the PON-
RES circuit operates when the horizontal supply voltage rises, the on/off bit must be set to off (0).)
2. Note on video muting
If the horizontal output pulse signal was stopped, after performing the operation described in paragraph 1 above, clear
the video muting bit to 0.
(This is because the video muting bit is forcibly set to 1 when the on/off bit is set to 0 or when either the x-ray
protection circuit or the PON-RES circuit operate. This also applies at power on.)
No. 5841-28/39
LA7615
A10074
Signal inappropriate for use as a sync input
Chrominance signal
Signal appropriate for use as a sync input
Burst signal