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參數(shù)資料
| 型號(hào)： | LA7615 |
| 元件分類(lèi)： | 消費(fèi)家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PDIP64 |
| 封裝： | SDIP-64 |
| 文件頁(yè)數(shù)： | 9/39頁(yè) |
| 文件大小： | 206K |
| 代理商： | LA7615 |
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No. 5841-17/39
LA7615
(Test Conditions)
Parameter
Symbol
Test point
Input signal
Test procedure
Bus condition
[VIF Block]
No signal AFT output voltage
No signal video output voltage
APC pull-in range (U), (L)
Maximum RF AGC voltage
Minimum RF AGC voltage
Video output amplitude
RF AGC Delay Pt
(@DAC = 0)
RF AGC Delay Pt
(@DAC = 63)
Input sensitivity
Video/Sync ratio
(@100 dB)
Differential gain
Differential phase
Video signal-to-noise ratio
Synchronizing signal tip level
4.5 MHz attenuation
920 kHz beat level
Maximum AFT output voltage
Minimum AFT output voltage
AFT detection sensitivity
V14
V53
fPU, fPL
V4H
V4L
VO53
RFAGC0
RFAGC63
VIN
V/S
DG
DP
S/N
V53 TIP
TRAP
I920
V14H
V14L
Sf
No signal
SG4 93 dB
SG1
91 dB
SG1
91 dB
SG7
93 dB
SG1
SG7
100 dB
SG5
93 dB
SG5
93 dB
SG1
93 dB
SG1
93 dB
SG6
93 dB
SG1
SG2
SG3
SG4
93 dB
44.75 MHz
SG4
93 dB
46.75 MHz
SG4
93 dB
Connect the pin 11 to ground and measure the pin
14 DC voltage.
Connect the pin 11 to ground and measure the pin
53 DC voltage.
Monitor pin 53 with an oscilloscope, and modify SG4
to have a frequency higher than 45.75 MHz so that
the PLL goes to the unlocked state. (Beating should
appear at this point.) Gradually decrease the SG4
frequency until the PLL circuit locks, and measure
the lock frequency.
Also, and modify SG4 to have a frequency lower
than 45.75 MHz so that the PLL goes to the
unlocked state. Gradually increase the SG4
frequency until the PLL circuit locks, and measure
the lock frequency.
Set the RF AGC D/A converter to 0 and measure the
pin 4 DC voltage.
Set the RF AGC D/A converter to 63 and measure
the pin 4 DC voltage.
Monitor the pin 53 with an oscilloscope, and
measure the peak-to-peak value of the waveform.
Set the RF AGC D/A converter to 0 and determine
the input level such that the pin 4 DC voltage
becomes 3.8 ±0.5 V.
Set the RF AGC D/A converter to 63 and determine
the input level such that the pin 4 DC voltage
becomes 3.8 ±0.5 V.
Monitor the pin 53 with an oscilloscope, and
measure the peak-to-peak value of the waveform.
Gradually decrease the input level and determine the
input level such that the output goes down to a level
lower than the video amplitude (VO 53) by –3 dB.
Monitor the pin 53 with an oscilloscope, and
measure the peak-to-peak values of the sync
waveform (Vs) and the luminance signal (Vy) to
determine the ratio Vy/Vs.
Measure the pin 53 with a vectorscope.
Pass the noise voltage signal generated at pin 53
through a 4 to 10 MHz bandpass filter and measure
that signal(Vsn) with an rms voltmeter. Determine the
value of the formula 20log(1.43/Vsn).
Measure the pin 53 DC voltage.
Measure the values of the 100 kHz and 4.5 MHz
components and determine their ratio.
Input the 93 dB SG1 signal, and measure the pin
11 DC voltage (V11). Mix the three signals SG1 = 87
dB, SG2 = 82 dB, and SG3 = 63 dB, and input
that signal to VIF IN. Apply the voltage V11 to pin 11
using an external power supply. Measure the
difflerence of the 3.58 MHz and 920 kHz
components using a spectrum analyzer.
Measure the pin 14 DC voltage.
Gradually change the SG4 frequency and
determined the frequency change
f required to
change the pin 14 DC voltage from 2.5 V to 5.0 V.
Sf = 2500/
f [mV/kHz]
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
The adjusted values
from item 4.
14
53
4
53
4
53
14
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