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參數(shù)資料
型號(hào): LC74950BG
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類(lèi): 消費(fèi)家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝: 6 X 6 MM, FBGA-96
文件頁(yè)數(shù): 25/37頁(yè)
文件大小: 350K
代理商: LC74950BG
LC74950BG
No.A1647-31/37
9. External interface
I
2C: 100kHz mode is supported. The slave address can be selected using the pin settings.
Slave address: 0x98, 0x9A
1) Control specifications
Slave operations in the standard mode (100kHz) are supported.
These must be used for setting the internal registers and setting the internal status output and
γ correction
characteristics. The slave addresses are listed in the table below. Two addresses can be selected using the I
2CSEL pin.
Slave address:
(I
2CSEL=0)
Slave address:
(I
2CSEL=1)
2) Control and timing specifications
(1) Receive mode
As shown below, the slave address W, sub-address and input data must be set in this sequence after the start
condition. The data of each sub-address can be input in auto address increments consecutively from the data of the
sub-address specified. The data must be set consecutively with ACK between one data and the next. The stop
condition must be set last.
Parameter
Symbol
min
max
unit
SCL clock frequency
fSCL
0
100
kHz
Start condition hold time
tH_S
4.0
μs
Data hold time
tH_D
0
μs
Data setup time
tS_D
250
ns
SDA and SCL rise time
tR
1000
ns
SDA and SCL fall time
tF
300
ns
SCL high level hold time
tHI
4.0
μs
SCL low level hold time
tLO
4.7
μs
Stop condition setup time
tS_P
4.7
μs
SDA
SCL
Slave address W
Sub-address
Input data
tH_S
tH_D
tS_D
tR tF
tHI tLO
tS_P
1
8
9
ACK
1
0
1
0
R/W
1
0
1
0
1
R/W
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