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參數資料
型號: LC74950BG
廠商: SANYO SEMICONDUCTOR CO LTD
元件分類: 消費家電
英文描述: SPECIALTY CONSUMER CIRCUIT, PBGA96
封裝: 6 X 6 MM, FBGA-96
文件頁數: 29/37頁
文件大小: 350K
代理商: LC74950BG
LC74950BG
No.A1647-35/37
PDOWN
Complete power-down can be controlled using the PDWN pin. ADC, PLL and other items can be powered down
individually by means of register settings. This makes it possible to limit the power consumption as required.
Internal states based on the PDWN pin setting
PDWN
ADC
PLL
Logic
Communication
Remarks
0
PowerDown
Clocks stopped
Stopped
Registers reset state
1
Operating
Power Down control by controlling registers
Item
ADC
Power-down can be controlled using dedicated registers. See below for the relevant registers.
PLL
Power-down can be controlled using dedicated registers. See below for the relevant registers.
Logic
External input is selected and the external clock is stopped.
Similarly, the clock is stopped by selecting the PLL mode and power down the PLL circuit.
Output pin
Output-enable (Hi-Z) can be set by using the dedicated registers.
Communication
Cannot be stopped.
Name
Functions
Sub address
bit width
STBL_Y
STBL_B
STBL_R
These registers control the ADC standby mode (Y: STBL_Y, B: STBL_B, R: STBL_R).
0000: ADC standby mode
1111: ADC normal operating mode
*1: Any other setting than above inhibited.
*2: These must be set in accordance with the operating mode of AEC.
0x21
0x23
0x25
4
STBB
This register controls the band gap VREF circuit.
0: Places the band gap VREF circuit into the standby mode.
1: Places the band gap VREF circuit into the normal operating mode.
*: This must be set in accordance with the operating mode of ADC.
0x21
1
STBB_Y
STBB_B
STBB_R
These registers control the AFE standby mode (Y: STBB_Y, B: STBB_B, R: STBB_R).
0: AFE standby mode
1: AFE normal operating mode
*: These must be set in accordance with the operating mode of ADC.
0x21
0x23
0x25
1
PLLCTL2
This register controls the H-lock PLL power down mode
0: Normal operating mode
1: H-lock PLL power off
0x27
1
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相關代理商/技術參數
參數描述
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