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參數資料
| 型號： | LC749870LG |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | 5 X 5 MM, FLGA-64 |
| 文件頁數： | 21/44頁 |
| 文件大小： | 538K |
| 代理商： | LC749870LG |
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LC749870LG
No.A1765-28/44
Functional Descriptions
1. CPU I/F
The LC749870LG registers are controlled by I2C.
1) I2C
The LC749870LG supports high-speed mode slave operation (400kHz) and the slave address is as follows.
bit[7]
(MSB)
bit[6]
bit[5]
bit[4]
bit[3]
bit[2]
bit[1]
bit[0]
(LSB)
1
0
1
0
I
2CSEL
R/W
*Note: The bit 1 is decided according to the I2CSEL pin condition.
bit 0 R/W: 0 = write, 1 = read
■Write Mode
Auto address increment.
As shown below, after the start condition, the settings must be made in the following order: slave address (W), ACK
waiting, write start sub address, ACK waiting, write data. The stop condition must be set last. Data can be transmitted
continuously from the write start sub address using the auto address increment function.
[ST] [Slave Address(W)] [A] [Sub address] [A] [Data] [A] [Data] [SP]
■Read Mode
Auto address increment.
The read start sub address must be assigned in write mode.
As shown below, after the start condition, first set the slave address (W), ACK waiting and read start sub address. Next,
set the start condition again or set the start condition after setting the stop condition. Next set the slave address (R) and
ACK waiting in read mode. The data for each sub address is output continuously from the read start sub address data
using the auto address increment function. After receiving the data for each sub address, return the ACK. Finally, set the
stop condition.
[ST] [Slave Address (W)] [A] [Sub address] [ST] [Slave Address(R)] [A] [Data] [A] [Data] [A] [Data] [SP]
or
[ST] [Slave Address (W)] [A] [Sub address] [SP] [ST] [Slave Address(R)] [A] [Data] [A] [Data] [A] [Data] [SP]
[ST]: Start condition
[SP]: Stop condition
[A]: ACK
[A]: ACK waiting
[Data]: Data transmission
[Data]: Data reception
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相關代理商/技術參數 |
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