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參數資料
| 型號： | LC82161B-E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁數： | 10/19頁 |
| 文件大小： | 225K |
| 代理商： | LC82161B-E |
LC82161B-E
No.7775-18/19
USART
The LC82161B provides two built-in USART (Universal synchronous/asynchronous receiver transmitter) circuits for
serial data communication.
Synchronous/asynchronous functions
— Synchronous mode
Character length: 5 to 8 bits
Internal or external synchronization
One or two character synchronization (internal synchronization)
Automatic synchronization character insertion
— Asynchronous mode:
Character length: 5 to 8 bits
Clock rate: 1×, 16×, or 64×
Stop bits: 1, 1.5, or 2
Break character transmission
False start bit detection
Automatic break state detection
Full-duplex, double FIFO system (reception: 16 bytes, transmission: 4 bytes)
Detection of parity, overrun, and framing errors
Built-in baud rate generators (Independent send and receive system circuits. Can be switched with an external clock.)
Baud rate: 7.7K to 3.2M baud (when a 51.2 MHz clock is used)
SIO
The LC82161B provides a single-channel clock synchronous 3-wire full-duplex serial interface.
Single-channel synchronous serial interface
Transfer clock selection function
— Internal clock (with variable clock period)
— External clock
Transfer clock polarity switching function
The polarity of the serial interface transfer clock can be switched. The level (high or low) of the SCK pin when no
communication operation is being performed can be set.
Data length switching function
— 8-bit transfers
— 16-bit transfers
Transfer bit length control function
— Single-frame (8 or 16 bits) transfers
— Continuous transfers
LSB first/MSB first switching function
Error detection function
— Overrun errors
— Receive register overwrite error
Divided Clock Signal Output
A divided clock signal with a frequency in the range 12.2 Hz to 800 kHz can be output from the DIVCK pin.
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