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參數資料
| 型號： | LC82161B-E |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP208 |
| 封裝： | SQFP-208 |
| 文件頁數： | 4/19頁 |
| 文件大?。?/td> | 225K |
| 代理商： | LC82161B-E |
LC82161B-E
No.7775-12/19
DSP
The DSP used in this IC is the Sanyo-designed FAVOR40 DSP. This DSP includes a built-in 24K-word program RAM and
a 16K-word data RAM. The DSP program is downloaded from external flash memory to DSP program RAM by the ARM7
after power is first applied. The CPU and the DSP interface using a 2K × 16-bit dual-ported RAM.
All DSP functions are provided as a CPU API program library. The following functions are provided by this API.
DSP reset
DSP program load/verify
DSP start
Codec settings (G.729A, G.711)
Jitter control settings
Echo canceller settings
Transmission packet readout
Received packet write
3 way conferencing settings
Melody output settings (3-tone harmony)
Tone/DTMF/RBT transmission settings
Tone/DTMF detection settings
V.23 transmission settings
V.23 reception settings
System Control Block
The system control block controls the system clock and the power saving mode of the various blocks.
DSP clock frequency settings
Power saving mode control (DSP and CPU clock divisor settings)
Peripheral block power saving mode control
DSP power saving mode settings and power saving mode recovery control
Memory Controller
The memory controller controls CPU external memory access.
External address space can be divided into areas 0 to 3 and each area can be set up independently.
— Chip select outputs (CS0n to CS3n) for each area, 0 to 3
— Selection of 8-bit or 16-bit access (areas 1 to 3)
— Selection of 16-bit or 32-bit access (area 0)
Cycle count settings (0 to 7 cycles) for address setup (Tacs) relative to chip select, for chip select setup (Tcos) relative to
output enable (write enable), and for chip select hold (Tcoh) relative to output enable (write enable).
Output enable (write enable) wait state settings
— Programmable wait states (0 to 15 wait states, 1 to 16 cycles, can be set up)
Support for both little endian and big endian
Minimum 1 wait state (2 cycles) access for write operations
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