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參數資料
| 型號： | LC89058W-E |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數： | 25/46頁 |
| 文件大小： | 284K |
| 代理商： | LC89058W-E |
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LC89058W-E
No.A1056-31/64
10.3.3 Output data switching (SDIN, RDATA)
RDATA outputs demodulation data when the PLL is locked, and outputs SDIN input data when the PLL is unlocked.
This output is automatically switched according to the PLL locked/unlocked status. For details, see the timing charts
below.
When SDIN input data is selected, switch to a clock source synchronized to the SDIN data.
With the RDTSTA setting, the SDIN input data is output to RDATA regardless of the locked/unlocked status of the
PLL.
With the RDTMUT setting, the RDATA output data can be also muted forcibly.
Even when the clock source is set to XIN with OCKSEL and RCKSEL, the PLL continues operating as long as the
PLL is not stopped with PLLOPR. At this time, the PLL status is continuously output from RERR unless error output
is forcibly set with RESTA. Moreover, the processed information can be read with the microcontroller interface
regardless of the PLL status.
Figure 10.10 Timing Chart of RDATA Output Data Switching
PLL status
CKST
RERR
(a): Lock-in stage
UNLOCK
LOCK
SDIN data
Muted
Demodulation data
RDATA
CKSTP=0
(b): Unlock stage
PLL status
CKST
RERR
LOCK
UNLOCK
SDIN data
Muted
Demodulation data
RDATA
CKSTP=0
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