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參數資料
| 型號： | LC89058W-E |
| 廠商： | SANYO SEMICONDUCTOR CO LTD |
| 元件分類： | 消費家電 |
| 英文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP48 |
| 封裝： | 7 X 7 MM, SQFP-48 |
| 文件頁數： | 31/46頁 |
| 文件大小： | 284K |
| 代理商： | LC89058W-E |
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LC89058W-E
No.A1056-37/64
11.3.2 GPIOS=1
The figure below shows the relationship between GPIO0, GPIO1, GPIO2, GPIO3 which are input to the selector and
the DIR block signal, and RMCK, RBCK, RLRCK, RDATA which are output from the selector and the control signal.
Figure 11.1 Selector Configuration Diagram
Table 11.1 Selector I/O Signals
Input Pin or Input Signal
EXTSEL=0
EXTSEL=1
PLL Lock State
PLL Unlock State
Output pin
GPIO0 (pin 44)
PLL-MCK
XIN-MCK
RMCK (pin 16)
GPIO1 (pin 45)
PLL-BCK
XIN-BCK
RBCK (pin 17)
GPIO2 (pin 46)
PLL-LRCK
XIN-LRCK
RLRCK (pin 20)
GPIO3 (pin 47)
PLL-DATA
SDIN
RDATA (pin 21)
Note: The selector output generated when the PLL is locked can be changed to the XIN clock system by setting the
OCKSEL and RCSEL.
EXTSEL is enabled by setting GPIOS=1. When GPIOS=0 is set, the state of EXTSEL=0 is output from each pin.
The clock input to GPIO0 can be inverted by EMCKP and sent to RMCK.
The data to be input to GPIO3 must conform to the PLL-DATA or SDIN audio format.
The data input to GPIO3 can be muted by EDTMUT.
EMCKP and EDTMUT are enabled when GPIOS=1 is set.
The above settings are valid only when the master mode is set and must not be set when the slave mode is set.
4
GPIO0
GPIO3
GPIO2
GPIO1
44
45
46
47
4
SDIN
24
DIR
PLL-MCK
PLL-DATA
PLL-LRCK
PLL-BCK
XIN-MCK
XIN-LRCK
XIN-BCK
4
RMCK
RDATA
RLRCK
RBCK
16
17
20
21
Lock judgment
4
“EXTSEL”
XM
radio
ADC
“EMCKP”
“EDTMUT”
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