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參數資料
| 型號： | LM1247AAG/NA/NOPB |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 音頻／視頻放大 |
| 英文描述： | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| 封裝： | PLASTIC, DIP-24 |
| 文件頁數： | 30/48頁 |
| 文件大小： | 3141K |
| 代理商： | LM1247AAG/NA/NOPB |
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Control Register Definitions (Continued)
Display Window 2 Horizontal Start Position:
HSTRT2 (0x8418)
Window 2 Horizontal Start Position
2H[7:0]
Bits 7–0
This register determines the horizontal start position of Window 2 in OSD pixels (not video signal pixels). The
actual position, to the right of the horizontal flyback pulse, is determined by multiplying this register value by 4
and adding 30. Due to pipeline delays, the first usable start location is approximately 42 OSD pixels following
the horizontal flyback time. For this reason, we recommend this register be programmed with a number larger
than 2, otherwise improper operation may result.
Display Window 2 Vertical Start Position:
VSTRT2 (0x8419)
Window 2 Vertical Start Position
2V[7:0]
Bits 7–0
This register determines the Vertical start position of Window 2 in constant-height character lines (not video
scan lines). The actual position is determined by multiplying this register value by 2. (Note: each character line
is treated as a single auto-height character pixel line, so multiple scan lines may actually be displayed in order
to maintain accurate position relative to the OSD character cell size. (See the Constant Character Height
Mechanism section.) This register should be set so the entire OSD window is within the active video.
Display Window 2 Start Address:
W2STRTADRH (0x841B)
W2STRTADRL (0x841A)
Reserved
Window 2 Start Address
X
XXXXXX
2AD[8:0]
Bits 8–0
This register determines the starting address of Display Window 2 in the Display Page RAM. The power-on
default of 0x100 starts Window 2 at the midpoint of the Page RAM (0x8100). This location always contains the
SL code for the first line of Window 2.
Bits 15–9
These bits are reserved and should be set to zero.
Display Window 2 Column Width:
COLWIDTH2B3 (0x841F)
COLWIDTH2B2 (0x841E)
Window 2 Column Width - High Bytes
COL[31:16]
COLWIDTH2B1 (0x841D)
COLWIDTH2B0 (0x841C)
Window 2 Column Width - Low Bytes
COL[15:0]
Bits 31–0
These are the Display Window 2 Column Width 2x Enable Bits. These thirty-two bits correspond to columns
31–0 of Display Window 2, respectively. A value of zero indicates the column will have normal width (12 OSD
pixels). A value of one indicates the column will be twice as wide as normal (24 OSD pixels). For the double
wide case, each Character Font pixel location will be displayed twice, in two consecutive horizontal pixel
locations. The user should note that if more than 32 display characters are programmed to reside on a row,
then all display characters after the first thirty-two will have normal width (12 pixels).
ROM Bank Select Register A:
BANKSEL_0-1 (0x8427)
Res’d
Bank Select 1
Res’d
Bank Select 0
X
B1AD[2:0]
X
B1AD[2:0]
Bits 2–0
This three bit field determines the ROM bank (0-7) selected when the upper two bits of the
character address in Page RAM are 00 (Character Address = 00xxxxxxb)
Bit 3
This bit is reserved and should be set to 0.
LM1247
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相關PDF資料 |
PDF描述 |
|---|---|
| LM1253AAE/NA | ON-SCREEN DISPLAY IC, PDIP28 |
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| LM1269NA/NOPB | 3 CHANNEL, VIDEO PREAMPLIFIER, PDIP24 |
| LM1276AAA/NA | 1 CHANNEL, VIDEO PREAMPLIFIER, PDIP28 |
| LM1279AN/NOPB | 3 CHANNEL, VIDEO AMPLIFIER, PDIP20 |
相關代理商/技術參數 |
參數描述 |
|---|---|
| LM1247DMC/NA | 制造商:Texas Instruments 功能描述: |
| LM124A | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low Power Quad Operational Amplifiers |
| LM124AD | 制造商:STMICROELECTRONICS 制造商全稱:STMicroelectronics 功能描述:LOW POWER QUAD OPERATIONAL AMPLIFIERS |
| LM124ADR | 制造商:TI 制造商全稱:Texas Instruments 功能描述:QUADRUPLE OPERATIONAL AMPLIFIERS |
| LM124ADT | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Voltage-Feedback Operational Amplifier |
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