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參數資料
| 型號： | LMX2301TMX |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | XO, clock |
| 英文描述： | PLLatinumTM 160 MHz Frequency Synthesizer for RF Personal Communications |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 160 MHz, PDSO20 |
| 封裝： | 0.173 INCH, PLASTIC, TSSOP-20 |
| 文件頁數： | 6/14頁 |
| 文件大小： | 225K |
| 代理商： | LMX2301TMX |
Functional Description
The simplified block diagram below shows the 19-bit data register, the 14-bit R Counter and the R15 Latch, and the 11-bit
N Counter (intermediate latches are not shown). The data stream is clocked (on the rising edge) into the DATA input, MSB first.
If the Control Bit (last bit input) is HIGH, the DATA is transferred into the R Counter (programmable reference divider) and the
S Latch (power up counter reset). If the Control Bit (LSB) is LOW, the DATA is transferred into the N Counter (programmable
divider).
TL/W/12458–1
PROGRAMMABLE REFERENCE DIVIDER (R COUNTER) AND COUNTER RESET (R15 LATCH)
If the Control Bit (last bit shifted into the Data Register) is HIGH, data is transferred from the 19-bit shift register into a 14-bit
latch (which sets the 14-bit R Counter) and the 1-bit R15 Latch, which can be used to force an immediate load of the R and N
counters during a cold power up condition. Serial data format is shown below.
TL/W/12458–14
14-BIT PROGRAMMABLE REFERENCE DIVIDER RATIO
(R COUNTER)
Divide
Ratio
R
14
R
13
R
12
R
11
R
10
R
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
0
#
1
#
0
#
0
#
16383
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
Divide ratio: 3 to 16383
R1 to R14: These bits select the divide ratio of the programmable
reference divider.
C: Control bit (set to HIGH level to load R counter and R15 Latch)
Data is shifted in MSB first.
1-BIT COUNTER RESET
(R15 LATCH)
Counter
Reset
R
15
Remove
Forced Load
0
Force
Load State
1
The 1-bit counter reset latch controls
whether the R and N counters are im-
mediately forced to load conditions
upon power up. If R
[
15
]
e
HIGH, the
N and R latch states are immediately
read into the respective counters.
SUGGESTED PROGRAMMING SEQUENCE AFTER COLD POWER-UP
1. Program N counter with desired divide ratio.
2. Program R counter with R15
e
1 and desired divide ratio. (N and R counters hold at load state.)
3. Program R counter with R15
e
0 and desired divide ratio. (N and R counters start counting.)
http://www.national.com
6
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相關代理商/技術參數 |
參數描述 |
|---|---|
| LMX2305 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:PLLatinumTM 550 MHz Frequency Synthesizer for RF Personal Communications |
| LMX2305 WAF | 制造商:Texas Instruments 功能描述: |
| LMX2305C WAF | 制造商:Texas Instruments 功能描述: |
| LMX2305TM | 制造商:Rochester Electronics LLC 功能描述: |
| LMX2305TMX | 功能描述:IC FREQ SYNTH DUAL 20-TSSOP RoHS:否 類別:集成電路 (IC) >> 時鐘/計時 - 時鐘發生器，PLL，頻率合成器 系列:PLLatinum™ 標準包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時鐘 輸出:時鐘 電路數:1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應商設備封裝:* 包裝:* |
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