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參數資料
型號： LT3507HUHF#TRPBF
廠商： Linear Technology
文件頁數： 10/28頁
文件大小： 302K
描述： IC REG QD BUCK/LINEAR 38-QFN
產品培訓模塊： More Information on LDOs
標準包裝： 2,500
拓撲： 降壓（降壓）（1），線性（LDO）（1）
功能： 任何功能
輸出數： 4
頻率 - 開關： 900kHz ~ 1.1MHz
電壓/電流 - 輸出 1： 0.8 V ~ 32.4 V，2.4A
電壓/電流 - 輸出 2： 0.8 V ~ 32.4 V，1.5A
電壓/電流 - 輸出 3： 0.8 V ~ 32.4 V，1.5A
帶 LED 驅動器： 無
帶監控器： 無
帶序列發生器： 是
電源電壓： 4 V ~ 36 V
工作溫度： -40°C ~ 150°C
安裝類型： 表面貼裝
封裝/外殼： 38-WFQFN 裸露焊盤
供應商設備封裝： 38-QFN（5x7）
包裝： 帶卷 (TR)
LT3507
10
3507fa
APPLICATIONS INFORMATION
STEP-DOWN CONSIDERATIONS
FB Resistor Network
The output voltage is programmed with a resistor divider
(refer to the Block Diagram) between the output and the
FB pin. Choose the resistors according to:
   
R1=R2
V
OUT
800mV
1
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
The parallel combination of R1 and R2 should be 10k or
less to avoid bias current errors.
Input Voltage Range
The minimum operating voltage is determined either by
the LT3507s internal undervoltage lockout (4V on V
IN1
, 3V
on V
IN2
 and V
IN3
) or by its maximum duty cycle. The duty
cycle is the fraction of time that the internal switch is on
and is determined by the input and output voltages:
   
DC=
V
OUT
+V
F
V
IN
V
SW
+V
F
where V
F
 is the forward voltage drop of the catch diode
(~0.4V) and V
SW
 is the voltage drop of the internal switch
(~0.3V at maximum load). This leads to a minimum input
voltage of:
   
V
IN(MIN)
=
V
OUT
+V
F
DC
MAX
V
F
+V
SW
The duty cycle is the fraction of time that the internal switch
is on during a clock cycle. The maximum duty cycle is
generally given by DC
MAX
 = 1 t
OFF(MIN)
" f
SW
. However,
unlike most  xed frequency regulators, the LT3507 will not
switch off at the end of each clock cycle if there is suf cient
voltage across the boost capacitor (C3 in Figure 1) to fully
saturate the output switch. Forced switch off for a minimum
time will only occur at the end of a clock cycle when the
boost capacitor needs to be recharged. This operation
has the same effect as lowering the clock frequency for a
 xed off time, resulting in a higher duty cycle and lower
minimum input voltage. The resultant duty cycle depends
on the charging times of the boost capacitor and can be
approximated by the following equation:
 
DC
MAX
=
1
1+
1
B
where B is the output current capacity divided by the typical
boost current from the BOOST pin current vs switch current
in the Typical Performance Characteristics section.
The maximum operating voltage without pulse-skipping
is determined by the minimum duty cycle DC
MIN
:
   
V
IN(PS)
=
V
OUT
+V
F
DC
MIN
V
F
+V
SW
with DC
MIN
 = t
ON(MIN)
 " f
SW
.
Thus both the maximum and minimum input voltages are
a function of the switching frequency and output voltages.
Therefore the maximum switching frequency must be set
to a value that accommodates all the input and output
voltage parameters and must meet both of the following
criteria for each channel:
 
 
f
MAX1
=
V
OUT
+V
F
V
IN(PS)
V
SW
+V
F
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
"
1
t
ON(MIN)
f
MAX2
= 1
V
OUT
+V
F
V
IN(MIN)
V
SW
+V
F
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
"
1
t
OFF(MIN)
The values of t
ON(MIN)
 and t
OFF(MIN)
 are functions of I
SW
 
and temperature (see chart in the Typical Performance
Characteristics section). Worst-case values for switch
currents greater than 0.5A are t
ON(MIN)
 = 130ns (for T
J
 >
125癈 t
ON(MIN)
 = 155ns) and t
OFF(MIN)
 = 170ns.
f
MAX1
 is the frequency at which the minimum duty cycle
is exceeded. The regulator will skip ON pulses in order to
reduce the overall duty cycle at frequencies above f
MAX1
.
It will continue to regulate but with increased inductor
current and greatly increased output ripple. The increased
peak inductor current in pulse-skipping will also stress
the switch transistor at high voltages and high switch-
ing frequency. If the LT3507 is allowed to pulse-skip and
the input voltage is greater than 20V, then the switching
frequency must be kept below 1.1MHz to prevent damage
to the LT3507.
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