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參數(shù)資料
| 型號： | MACH230-20JC |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High-Density EE CMOS Programmable Logic |
| 中文描述： | EE PLD, 20 ns, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 1/29頁 |
| 文件大?。?/td> | 230K |
| 代理商： | MACH230-20JC |
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Publication#
14132
Issue Date:
May 1995
Rev.
I
Amendment
/0
MACH230-10/15/20
High-Density EE CMOS Programmable Logic
FINAL
COM’L: -10/15/20
IND: -18/24
DISTINCTIVE CHARACTERISTICS
84 Pins
128 Macrocells
10 ns t
PD
Commercial
18 ns t
PD
Industrial
100 MHz f
CNT
70 Inputs
64 Outputs
128 Flip-flops; 4 clock choices
8 “PAL26V16” blocks with buried macrocells
Pin-compatible with MACH130, MACH131,
MACH231, and MACH435
GENERAL DESCRIPTION
The MACH230 is a member of
the
high-performance
EE CMOS MACH 2 device family. This device has ap-
proximately twelve times the logic macrocell capability
of the popular PAL22V10 without loss of speed.
The MACH230 consists of eight PAL blocks intercon-
nected by a programmable switch matrix. The switch
matrix connects the PAL blocks to each other and to all
input pins, providing a high degree of connectivity be-
tween the fully-connected PAL blocks. This allows
designs to be placed and routed efficiently.
The MACH230 has two kinds of macrocell: output and
buried. The output macrocell provides registered,
latched, or combinatorial outputs with programmable
polarity. If a registered configuration is chosen, the reg-
ister can be configured as D-type or T-type to help
reduce the number of product terms. The register type
decision can be made by the designer or by the soft-
ware. All output macrocells can be connected to an I/O
cell. If a buried macrocell is desired, the internal feed-
back path from the macrocell can be used, which frees
up the I/O pin for use as an input.
The MACH230 has dedicated buried macrocells which,
in addition to the capabilities of the output macrocell,
also provide input registers for use in synchronizing
signals and reducing setup time requirements.
BLOCK DIAGRAM
If you would like to view
Block Diagram in full size,
please click on the box.
Lattice Semiconductor
相關PDF資料 |
PDF描述 |
|---|---|
| MACH4-96 | High-Performance EE CMOS Programmable Logic |
| MACH4 | High Performance E 2 CMOS In-System Programmable Logic |
| MACH435Q-20JC | High-Density EE CMOS Programmable Logic |
| MACH435Q-25JC | High-Density EE CMOS Programmable Logic |
| MACH435-12 | High-Density EE CMOS Programmable Logic |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MACH231-10JC/1 | 制造商:Advanced Micro Devices 功能描述: |
| MACH231-12JC/1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH231-12JI/1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH231-14JI/1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
| MACH231-15JC/1 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High-Performance EE CMOS Programmable Logic |
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