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參數(shù)資料
| 型號： | MACH5 |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | Fifth Generation MACH Architecture |
| 中文描述： | 第五代馬赫架構(gòu) |
| 文件頁數(shù)： | 1/47頁 |
| 文件大小： | 1145K |
| 代理商： | MACH5 |
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Publication#
20446
Amendment/
0
Rev:
I
Issue Date:
September 2000
MACH
5 CPLD Family
Fifth Generation MACH Architecture
FEATURES
N
High logic densities and I/Os for increased logic integration
— 128 to 512 macrocell densities
— 68 to 256 I/Os
N
Wide selection of density and I/O combinations to support most application needs
— 6 macrocell density options
— 7 I/O options
— Up to 4 I/O options per macrocell density
— Up to 5 density & I/O options for each package
N
Performance features to fit system needs
— 5.5 ns t
PD
Commercial, 7.5 ns t
PD
Industrial
— 182 MHz f
CNT
— Four programmable power/speed settings per block
N
Flexible architecture facilitates logic design
— Multiple levels of switch matrices allow for performance-based routing
— 100% routability and pin-out retention
— Synchronous and asynchronous clocking, including dual-edge clocking
— Asynchronous product- or sum-term set or reset
— 16 to 64 output enables
— Functions of up to 32 product terms
N
Advanced capabilities for easy system integration
— 3.3-V & 5-V JEDEC-compliant operations
— IEEE 1149.1 compliant for boundary scan testing
— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port
— PCI compliant (-5/-6/-7/-10/-12 speed grades)
— Safe for mixed supply voltage system design
— Bus-Friendly Inputs & I/Os
— Individual output slew rate control
— Hot socketing
— Programmable security bit
N
Advanced E
CMOS process provides high performance, cost effective solutions
N
Supported by ispDesignEXPERT software for rapid logic development
— Supports HDL design methodologies with results optimized for MACH 5 devices
— Flexibility to adapt to user requirements
— Software partnerships that ensure customer success
N
Lattice and Third-party hardware programming support
— LatticePRO software for in-system programmability support on PCs and Automated Test
Equipment
— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,
and System General
2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MACHLV210-12 | High Density EE CMOS Programmable Logic |
| MACHLV210-12JC | High Density EE CMOS Programmable Logic |
| MACHLV210-15JC | High Density EE CMOS Programmable Logic |
| MACHLV210-20JC | High Density EE CMOS Programmable Logic |
| MAF00009AEM | Cascade connection possible (usable as a 16-bit to 32-bit timer) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MACH5-256/68-7YC-10YI | 制造商:Advanced Micro Devices 功能描述: |
| MACHLV210-12 | 制造商:LATTICE 制造商全稱:Lattice Semiconductor 功能描述:High Density EE CMOS Programmable Logic |
| MACHLV210-12JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACHLV210-15JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| MACHLV210-20JC | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Lattice Semiconductor Corporation 功能描述: |
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