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| 型號： | MAX5938LEEE+ |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 21/26頁 |
| 文件大小： | 915K |
| 描述： | IC HOT-SWAP CTRLR -48V 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | -10 V ~ -80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 管件 |
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Power-Up-to-Fault-Management Fault:
1) Same as step 1 above. [GATE turn-on]
2) Same as step 2 above. [V
OUT
ramp]
3) GATE ramps to 90% of full enhancement while
V
OUT
remains above 74% V
CB
, at which point the
GATE is rapidly pulled to V
EE
and fault manage-
ment is initiated. [Fault management]
GATE Cycle During V
IN
Step
A step GATE cycle occurs only after a successful
power-up GATE cycle to full enhancement occurs and
as a result of a positive V
IN
step (all voltages are
relative to V
EE
).
Step-to-Full-Enhancement Fault:
1) A V
IN
step occurs resulting in STEP_MON rising
above STEP
TH
before V
OUT
rises above V
SC
. [Step
detection]
2) After a step is detected, V
OUT
rises above V
SC
in
response to the step. When V
OUT
rises above V
SC
,
GATE is immediately pulled to V
EE
, rapidly turning
off the power MOSFET. GATE is held at V
EE
for
350祍 to damp any ringing. Once GATE is pulled to
V
EE
, the gate cycle has begun and STEP_MON can
safely drop below STEP
TH
and successfully com-
plete a step GATE cycle to full enhancement without
initiating fault management. [GATE pulldown]
3) Following the 350祍 of GATE pulldown, GATE is
allowed to float for 650祍. At this point, the GATE
begins to ramp with 52礎(chǔ) charging the gate of the
power MOSFET. [GATE turn-on]
4) When GATE reaches the gate threshold voltage of
the power MOSFET, V
OUT
begins to ramp down
toward the new lower V
EE
. In the interval where
GATE is below the MOSFET threshold, the MOSFET
is off and V
OUT
will droop depending on the RC
time constant of the load. [V
OUT
ramp]
5) When V
OUT
ramps below 74% V
CB
, the GATE pulls
rapidly to full enhancement and the step GATE
cycle is complete. If STEP_MON remains above
STEP
TH
when GATE has ramped to 90% of full
enhancement and V
OUT
remains above 74% of V
CB
,
GATE remains at 90% and is not pulled to full
enhancement. In this condition, if V
OUT
drops below
74% of V
CB
before STEP_MON drops below
STEP
TH
, GATE is rapidly pulled to full enhancement
and the step GATE cycle is complete. PGOOD
remains asserted throughout the step GATE cycle.
[Full enhancement]
Step-to-Fault-Management Fault:
1) Same as step 1 above. [Step detection]
2) Same as step 2 above. [GATE pulldown]
3) Same as step 3 above. [GATE turn-on]
4) Same as step 4 above. [V
OUT
ramp]
5) If STEP_MON is below STEP
TH
when GATE ramps
to 90% of full enhancement and V
OUT
remains
above 74% V
CB,
GATE is rapidly pulled to V
EE
.
Fault management is initiated and PGOOD is de-
asserted. If STEP_MON is above STEP
TH
when
GATE ramps to 90% of full enhancement and V
OUT
remains above 74% of V
CB
, GATE remains at 90%.
It is not pulled to full enhancement nor is it pulled to
V
EE
. In this condition, if V
OUT
drops below 74% of
V
CB
before STEP_MON drops below STEP
TH
,
GATE is rapidly pulled to full enhancement and a
fault is avoided. Conversely, if STEP_MON drops
below STEP
TH
first, the GATE is rapidly pulled to
V
EE
, fault management is initiated, and PGOOD is
deasserted. [Fault management]
It should be emphasized that while STEP_MON remains
above STEP
TH
the current fault management is
blocked. During this time it is possible for there to be
multiple events involving V
OUT
rising above V
SC
then
falling below 74% V
CB
. In each of these events, when
V
OUT
rises above V
SC
, a full GATE cycle is initiated
where GATE is first pulled low then allowed to ramp up.
Then finally, when V
OUT
conditions are met, it will be
fully enhanced.
GATE Cycle During Momentary Overvoltage
An OV GATE cycle occurs only after a successful
power-up GATE cycle to full enhancement and as a
result of a momentary excursion of OV above the OV
threshold voltage. An OV GATE cycle does not result in
an OV fault unless OV remains above the threshold for
more than 1.5ms (all voltages are relative to V
EE
).
OV GATE Cycle to Full enhancement:
1) When OV rises above the OV threshold voltage,
GATE is immediately pulled to V
EE
, rapidly turning
off the power MOSFET. GATE is held at V
EE
indefi-
nitely while OV is above the OV threshold voltage. It
is held for an additional 350祍 to damp any ringing.
[GATE pulldown]
2) Following the GATE pulldown, GATE is allowed to
float for 650祍. At this point, the GATE begins to
ramp with 52礎(chǔ) charging the gate of the power
MOSFET. [GATE turn-on]
-48V Hot-Swap Controller with V
IN
Step Immunity,
No R
SENSE
, and Overvoltage Protection
______________________________________________________________________________________ 21
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5938LEEE+ | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5938LEEE+T | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5938LEEE-T | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5939AESA | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5939AESA+ | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
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