- 您現(xiàn)在的位置：買賣IC網(wǎng) > Datasheet目錄43 > MAX5938LEEE+ (Maxim Integrated)IC HOT-SWAP CTRLR -48V 16-QSOP Datasheet資料下載
參數(shù)資料
| 型號(hào)： | MAX5938LEEE+ |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 23/26頁 |
| 文件大小： | 915K |
| 描述： | IC HOT-SWAP CTRLR -48V 16-QSOP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 100 |
| 類型： | 熱交換控制器 |
| 應(yīng)用： | 通用 |
| 內(nèi)部開關(guān)： | 無 |
| 電源電壓： | -10 V ~ -80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 管件 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當(dāng)前第23頁第24頁第25頁第26頁
-48V Hot-Swap Controller with V
IN
Step Immunity,
No R
SENSE
, and Overvoltage Protection
______________________________________________________________________________________ 23
V
CB
and V
SC
and they represent the minimum V
OUT
excursion required to trip the respective fault.
R
STEP_MON
will typically be set to 100k& ?%. This
gives a V
STEP_MON
of 0.25V, a worst-case low of
0.13V, and a worst-case high of 0.37V. In finding ?/DIV>
STEP
in the equation below, use V
STEP_MON
= 0.37V to
ensure sufficient margin with worst-case I
STEP_OS
.
To set ?/DIV>
STEP
to block all V
CB
and V
SC
faults for any
ramp rate, find the ratio of V
STEP_MON
to V
CB
and
choose ?/DIV>
STEP
so:
?/DIV>
STEP
= 1.2 x ?/DIV>
C
x V
STEP_MON
/ V
CB
and since R
STEP_MON
= 100k&:
C
STEP_MON
= ?/DIV>
STEP
/ R
STEP_MON
= ?/DIV>
主站蜘蛛池模板：
察隅县|
营口市|
绥阳县|
周口市|
巩留县|
武冈市|
云浮市|
江西省|
柳林县|
乳源|
阿图什市|
隆林|
松溪县|
大化|
常熟市|
泽库县|
海阳市|
尼勒克县|
南靖县|
上林县|
云龙县|
顺义区|
赤峰市|
沈阳市|
东丰县|
汉川市|
漯河市|
宜宾市|
南岸区|
四川省|
涪陵区|
伊春市|
滦南县|
阳城县|
洛南县|
桂东县|
涟水县|
庆城县|
洛阳市|
奇台县|
永城市|
STEP
/ 100k&
After the first-pass component selection, if sufficient
timing margin exists, it is possible (but not necessary)
to lower R
STEP
below 100k& to reduce the sensitivity of
STEP_MON to V
IN
noise.
Verification of the Step
Monitor Timing
It is prudent to verify conclusively that all circuit-breaker
and short-circuit faults will be blocked for all ramp
rates. To do this, some form of graphical analysis is
recommended but first, find the value of ?/DIV>
L,eqv
of the
load by a series of ramp tests as indicated earlier.
These tests include evaluating the load with a series of
V
IN
ramps of increasing ramp rates and monitoring the
rate of rise of V
OUT
during the ramp. Each V
IN
ramp
should have a constant slope. The V
OUT
response data
must be taken only during the positive ramp. Data
taken after V
IN
has leveled off at the new higher value
must not be used.
Figure 21 shows the load in parallel with the load
capacitor, C
LOAD
, and the parallel connection in series
with the power MOSFET, which is fully enhanced with
V
GS
= 10V. The objective is to determine ?/DIV>
L,eqv
from
the V
OUT
response.
Figure 22 shows the general response of V
OUT
to a V
IN
ramp over time t. Equation 1 gives the response of V
OUT
to a ramp of dV/dt. The product (dV/dt) x ?/DIV>
C
=
V
OUT
(max) or the maximum V
OUT
voltage differential if
the V
IN
ramp were to continue indefinitely. The parame-
ter of interest is V
OUT
due to the ramp dV/dt, thus it is
necessary to subtract the DC shift in V
OUT
due to the
load resistance. For some loads, which are relatively
independent of supply voltage, this may be insignificant.
V
OUT
(t) = V
OUT
(t) R
DS(ON)
x I
LOAD
where I
LOAD
is a function of the V
OUT
level that should
be determined separately with DC tests.
Figure 21. V
IN
Ramp Test Of Load
L
EQU
R
EQV
C
LOAD
LOAD
LOAD CAPACITOR
WITH PARASITICS
V
IN
RAMP
V
IN
= GND = V
EE
10V
R
DS,ON
V
IN
Figure 22. General Response of V
OUT
to a V
IN
Ramp
dv
dt
?/DIV>
C
dv
dt
V
IN
V
OUT
.F
V
OUT
i
V
IN
RAMP
0
t1 t2 t3 t4
Figure 23. V
OUT
Response to V
IN
Ramp of 300V/ms
V
OUT
RESPONSE TO V
IN
RAMP OF 300V/ms
TIME (祍)
7
6
4
5
2
3
1
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
0
0
8
A
B
d
VIN
dt
t
CB
t
SC
E
F
C
D
A = V
IN
(GND - V
EE
)
B = V
STEP_MON
C = V
OUT
D = V
STEP,TH
E = V
CB
F = V
SC
t
STEP
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MAX5939EESA+ | IC HOT-SWAP CTRLR -48V 8-SOIC |
| MAX5946LETX+T | IC CNTRLR PCI EXP DL 36TQFN |
| MAX5948BESA+T | IC CNTRLR HOT SWAP 8-SOIC |
| MAX5949BESA+T | IC CNTRLR HOT SWAP 8-SOIC |
| MAX5950ETJ+ | IC PWM CTRL HOT-SW 12V 32TQFN-EP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX5938LEEE+ | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5938LEEE+T | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5938LEEE-T | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5939AESA | 功能描述:熱插拔功率分布 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
| MAX5939AESA+ | 功能描述:熱插拔功率分布 48V- Hot-Swap Controller RoHS:否 制造商:Texas Instruments 產(chǎn)品:Controllers & Switches 電流限制: 電源電壓-最大:7 V 電源電壓-最小:- 0.3 V 工作溫度范圍: 功率耗散: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:MSOP-8 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。