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參數資料
| 型號： | MAX6622UE9A+T |
| 廠商： | Maxim Integrated |
| 文件頁數： | 3/18頁 |
| 文件大小： | 196K |
| 描述： | IC PREC TEMP MONITOR 5CH 16TSSOP |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 功能： | 溫度監控系統（傳感器） |
| 傳感器類型： | 內部和外部 |
| 感應溫度： | -40°C ~ 125°C，外部傳感器 |
| 精確度： | -0.1°C 本地，±3°C 遠程 |
| 拓撲： | ADC，緩沖器，寄存器庫 |
| 輸出類型： | SMBus? |
| 輸出警報： | 是 |
| 輸出風扇： | 是 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | -40°C ~ 125°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應商設備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
5-Channel Precision Temperature Monitor
_______________________________________________________________________________________ 3
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= +3.0V to +5.5V, V
STBY
= V
CC
, T
A
= -40癈 to +125癈, unless otherwise noted. Typical values are at V
CC
= +3.3V and
T
A
= +25癈.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
SMBus INTERFACE (SCL, SDA), STBY
Logic Input Low Voltage
V
IL
0.8
V
V
CC
= 3.0V
2.2
Logic Input High Voltage
V
IH
V
CC
= 5.0V
2.4
V
Input Leakage Current
-1
+1
礎
Output Low Voltage
V
OL
I
SINK
= 6mA
0.3
V
Input Capacitance
C
IN
5
pF
SMBus-COMPATIBLE TIMING (Figures 3 and 4) (Note 2)
Serial-Clock Frequency
f
SCL
(Note 3)
400
kHz
f
SCL
= 100kHz
4.7
Bus Free Time Between STOP
and START Condition
t
BUF
f
SCL
= 400kHz
1.6
祍
f
SCL
= 100kHz
4.7
START Condition Setup Time
f
SCL
= 400kHz
0.6
祍
90% of SCL to 90% of SDA,
f
SCL
= 100kHz
0.6
Repeat START Condition Setup
Time
t
SU:STA
90% of SCL to 90% of SDA,
f
SCL
= 400kHz
0.6
祍
START Condition Hold Time
t
HD:STA
10% of SDA to 90% of SCL
0.6
祍
90% of SCL to 90% of SDA,
f
SCL
= 100kHz
4
STOP Condition Setup Time
t
SU:STO
90% of SCL to 90% of SDA,
f
SCL
= 400kHz
0.6
祍
10% to 10%, f
SCL
= 100kHz
1.3
Clock Low Period
t
LOW
10% to 10%, f
SCL
= 400kHz
1.3
祍
Clock High Period
t
HIGH
90% to 90%
0.6
祍
f
SCL
= 100kHz
300
Data Hold Time
t
HD:DAT
f
SCL
= 400kHz (Note 4)
900
ns
f
SCL
= 100kHz
250
Data Setup Time
t
SU:DAT
f
SCL
= 400kHz
100
ns
f
SCL
= 100kHz
1
Receive SCL/SDA Rise Time
t
R
f
SCL
= 400kHz
0.3
祍
Receive SCL/SDA Fall Time
t
F
300
ns
Pulse Width of Spike Suppressed
t
SP
0
50
ns
SMBus Timeout
t
TIMEOUT
SDA low period for interface reset
25
37
45
ms
Note 1: All parameters are tested at T
A
= +85癈. Specifications over temperature are guaranteed by design.
Note 2: Timing specifications are guaranteed by design.
Note 3: The serial interface resets when SCL is low for more than t
TIMEOUT
.
Note 4: A transition must internally provide at least a hold time to bridge the undefined region (300ns max) of SCLs falling edge.
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