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參數資料
| 型號： | MB81N643289 |
| 廠商： | Fujitsu Limited |
| 英文描述： | DRILL BIT HIGH SPEED STEEL .021,1 |
| 中文描述： | 8 × 256K × 32位的雙倍數據速率FCRAMTM |
| 文件頁數： | 27/64頁 |
| 文件大小： | 1732K |
| 代理商： | MB81N643289 |
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27
MB81N643289-50/-60
Preliminary (AE1E)
I
RECOMMENDED OPERATING CONDITIONS (Continued)
Notes:
*3. V
REF
is expected to track variations in the DC level of V
DDQ
of the transmitting device.
Peak-to-Peak noise level on V
REF
may not exceed +/- 2% of the supplied DC value.
*4. V
ISO
means {V
IN(CLK)
+ V
IN(CLK)
} / 2. Refer to Differential Input Signal Definition.
WARNING:
Recommended operating conditions are normal operating ranges for the semiconductor device.
All the device’s electrical characteristics are warranted when operated within these ranges.
Always use semiconductor devices within the recommended operating conditions. Operation outside
these ranges may adversely affect reliability and could result in device failure.
No warranty is made with respect to uses, operating conditions, or combinations not represented on
the data sheet. Users considering application outside the listed conditions are advised to contact their
FUJITSU representative beforehand.
Differential Input Signal Definition
I
CAPACITANCE
(T
A
= 25
°
C, f = 1 MHz)
Max.
Parameter
Symbol
Min.
Typ.
Unit
Input Capacitance, Address & Control
C
IN1
2.5
—
3.5
pF
Input Capacitance, CLK & CLK
C
IN2
2.5
—
3.5
pF
Input Capacitance, DM
0
to DM
3
C
IN3
4.0
—
5.5
pF
I/O Capacitance
C
I/O
4.0
—
5.5
pF
*2. Undershoot limit: V
(min)
pulse width measured at 50% of pulse amplitude.
V
DD
+ 1V
VIH
VIH
min
VIL
Pulse width
≤
4 ns
*1. Overshoot limit: V
IH
(max)
= V
+ 1V for pulse width
<= 4 ns acceptable,
50% of pulse amplitude
VIH
VIL
-1.0V
pulse width measured at 50% of pulse amplitude.
= V
SS
1.0V for pulse width
<= 4 ns acceptable,
50% of pulse amplitude
Pulse width
≤
4 ns
VIL
max
Fig. 4 – Differential Input Signal Offset Voltage (For Clock Input)
V
ISO
(max.)
V
ISO
(min.)
CLK
V
SWING(AC)
V
X
CLK
V
SS
|V
SWING
|
0V Differential
V
ISO
V
SS
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