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參數資料
型號: MB84VP24491HK-70PBS
廠商: Fujitsu Limited
英文描述: RES NET BUSSED 150 OHM 6-SIP
中文描述: 128M的(x16)的快閃記憶體32M的(x16)的移動FCRAMTM
文件頁數: 48/70頁
文件大小: 1272K
代理商: MB84VP24491HK-70PBS
MB84VP24491HK
-70
47
WRITE OPERATION (32M Page mode FCRAM)
*1 : Maximum value is applicable if CE1r is kept at Low without any address change. If the relaxation is needed by
system operation, please contact local FUJITSU representative for the relaxation of 1
μ
s limitation.
*2 : Minimum value must be equal or greater than the sum of write pulse (t
CW
, t
WP
or t
BW
) and write recovery time
(t
WRC
, t
WR
or t
BR
).
*3 : Write pulse is defined from High to Low transition of CE1r, WE, or LB / UB, whichever occurs last.
*4 : Write recovery is defined from Low to High transition of CE1r, WE, or LB / UB, whichever occurs first.
*5 : Applicable to any address change when CE1r stays Low.
*6 : If OE is Low after minimum t
OHCL
, read cycle is initiated. In other word, OE must be brought to High within 5ns
after CE1r is brought to Low. Once read cycle is initiated, new write pulse should be input after minimum t
RC
is met.
*7 : If OE is Low after new address input, read cycle is initiated. In other word, OE must be brought to High at the
same time or before new address valid. Once read cycle is initiated, new write pulse should be input after
minimum t
RC
is met.
Parameter
Symbol
Value
Unit
Remarks
Min
Max
Write Cycle Time
t
WC
70
1000
ns
*1, *2
Address Setup Time
t
AS
0
ns
*2
CE1r Write Pulse Width
t
CW
45
ns
*3
WE Write Pulse Width
t
WP
45
ns
*3
LB / UB Write Pulse Width
t
BW
45
ns
*3
CE1r Write Recovery Time
t
WRC
15
ns
*4
WE Write Recovery Time
t
WR
15
1000
ns
*4
LB / UB Write Recovery Time
t
BR
15
1000
ns
*4
Data Setup Time
t
DS
20
ns
Data Hold Time
t
DH
0
ns
Address Invalid Time after Write
t
AXW
10
ns
*5
OE High to CE1r Low Setup Time for
Write
t
OHCL
–5
ns
*6
OE High to Address Setup Time
for Write
t
OES
0
ns
*7
LB and UB Write Pulse Overlap
t
BWO
20
ns
CE1r High Pulse Width
t
CP
15
ns
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