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參數資料
型號: MC34115DW
廠商: MOTOROLA INC
元件分類: 編解碼器
英文描述: CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR
中文描述: CVSD, CVSD CODEC, PDSO16
封裝: PLASTIC, SO-16
文件頁數: 11/16頁
文件大小: 359K
代理商: MC34115DW
MC34115
11
MOTOROLA ANALOG IC DEVICE DATA
Figure 15. 16 kHz Simplex Voice Codec
(Using MC34115, Single–Pole Companding and Single Integration)
Comp
1
Rmin
Push
To Talk
Key
Analog
Input
0.1
Analog
Out
5.0
(Norm
Open)
1.0 k
10 k
Clock
600
4.0
μ
F
Slope Polarity
Switch
Digital Input
Digital Output
Clock 16 kHz
Encode/Decode
VCC/2
Ref
0.33
18 k
RS
Syl
In
+
11
3.3 k RP
Coin
Out
+
+
2
13
12
10
5
7
Vth
600
1.3 k Rx
8
VEE
6
Filter
Ref
C1
R1
+
10 k
0.1
10 k
Digital
Out
16
GC
4
VS
5.0
Ref
Input
15
2.4 M
9
14 VCC
3
Shift
Register
Logic
CS
Analog
Output
APPLICATIONS INFORMATION
CVSD DESIGN CONSIDERATIONS
A simple CVSD encoder using the MC34115 is shown in
Figure 15. This IC is a general purpose CVSD building block
which allows the system designer to tailor the encoder’s
transmission characteristics to the application. Thus, the
achievable transmission capabilities are constrained by the
fundamental limitations of delta modulation and the design of
encoder parameters. The performance is not dictated by the
internal configuration of the MC34115. There are six design
considerations involved in designing these basic CVSD
building blocks into a specific codec application.
These are listed below:
1. Selection of clock rate
2. Selection of loop gain
3. Selection of minimum step size
4. Design of integration filter transfer function
5. Design of syllabic filter transfer function
6. Design of low pass filter at the receiver
The circuit in Figure 15 is the most basic CVSD circuit
possible. For many applications in secure radio or other
intelligible voice channel requirements, it is entirely sufficient.
In this circuit, items 4 and 5 are reduced to their simplest
form. The syllabic and integration filters are both single–pole
networks. The selection of items 1 through 3 govern the
codec performance.
Layout Considerations
Care should be exercised to isolate all digital signal paths
(Pins 9, 11, 13 and 14) from analog signal paths (Pins 1 to 7
and 10) in order to achieve proper idle channel performance.
Clock Rate
With minor modifications, the circuit in Figure 15 may be
operated anywhere from 9.6 to 64 kHz clock rates. Obviously
the higher the clock rate the higher the S/N performance. The
circuit in Figure 15 typically produces the S/N performance
shown in Figure 16. The selection of clock rate is usually
dictated by the bandwidth of the transmission medium. Voice
bandwidth systems will require no higher than 9600 Hz.
Some radio systems will allow 12 kHz. Private 4–wire
telephone systems are often operated at 16 kHz and
commercial telephone performance can be achieved at
32 k bits and above.
相關PDF資料
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相關代理商/技術參數
參數描述
MC34115P 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR
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MC34117D 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Telephone tone ringer
MC34117P 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:Telephone tone ringer
MC34118 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:Specifications and Applications Information
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