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參數資料
| 型號： | MC34115DW |
| 廠商： | MOTOROLA INC |
| 元件分類： | 編解碼器 |
| 英文描述： | CONTINUOUSLY VARIABLE SLOPE DELTA MODULATOR/DEMODULATOR |
| 中文描述： | CVSD, CVSD CODEC, PDSO16 |
| 封裝： | PLASTIC, SO-16 |
| 文件頁數： | 4/16頁 |
| 文件大小： | 359K |
| 代理商： | MC34115DW |
MC34115
4
MOTOROLA ANALOG IC DEVICE DATA
DEFINITION AND FUNCTION OF PINS
Pin 1 – Analog Input
This is the analog comparator inverting input where the
voice signal is applied. It may be ac or dc coupled depending
on the application. If the voice signal is to be level shifted to
the internal reference voltage, then a bias resistor between
Pins 1 and 10 is used. The resistor is used to establish the
reference as the new dc average of the ac coupled signal.
The analog comparator was designed for low hysteresis
(typically less than 0.1 mV) and high gain (typically 70 dB).
Pin 2 – Analog Feedback
This is the noninverting input to the analog signal
comparator. In an encoder application it should be
connected to the analog output of the encoder circuit. This
may be Pin 7 or a low pass filter output connected to Pin 7.
In a decode circuit, Pin 2 is not used and may be tied to
VCC/2 at Pin 10 or ground.
The analog input comparator has bias currents of 2.5
μ
A
max, thus the driving impedances of Pins 1 and 2 should be
equal to avoid disturbing the idle channel characteristics of
the encoder.
Pin 3 – Syllabic Filter
This is the point at which the syllabic filter voltage is
returned to the IC in order to control the integrator step size.
It is an NPN input to an op amp. The syllabic filter consists of
an RC network between Pins 11 and 3. Typical time constant
values of 6.0 ms to 50 ms are used in voice codecs.
Pin 4 – Gain Control Input
The syllabic filter voltage appears across CS of the syllabic
filter and is the voltage between VCC and Pin 3. The active
voltage to current (V–I) converter drives Pin 4 to the same
voltage at a slew rate of typically 0.5 V/
μ
s. Thus the current
injected into Pin 4 (IGC) is the syllabic filter voltage divided by
the Rx resistance. Figure 7 shows the relationship between
IGC (x–axis) and the integrating current, IInt (y–axis). The
discrepancy, which is most significant at very low currents, is
due to circuitry within the slope polarity switch which enables
trimming to a low total loop offset. The Rx resistor is then
varied to adjust the loop gain of the codec, but should be no
larger than 5.0 k
to maintain stability.
Pin 5 – Reference Input
This pin is the noninverting input of the integrator amplifier.
It is used to reference the dc level of the output signal. In an
encoder circuit, it must reference the same voltage as Pin 1
and is tied to Pin 10.
Pin 6 – Filter Input
This inverting op amp input is used to connect the
integrator external components. The integrating current (IInt)
flows into Pin 6 when the analog input (Pin 1) is high with
respect to the analog feedback (Pin 2) in the encode mode
or when the digital data input (Pin 13) is high in the decode
mode. For the opposite states, IInt flows out of Pin 6. Single
integration systems require a capacitor and resistor between
Pins 6 and 7. Multipole configurations will have different
circuitry. The resistance between Pins 6 and 7 should
typically be between 8.0 k
and 13 k
to maintain good idle
channel characteristics.
Pin 7 – Analog Output
This is the integrator op amp output. It is capable of driving
a 600
load referenced to VCC/2 to +6.0 dBm and can
otherwise be treated as an op amp output. Pins 5, 6 and 7
provide full access to the integrator op amp for designing
integration filter networks. The slew rate of the internally
compensated integrator op amp is typically 0.5 V/
μ
s. Pin 7
output is current limited for both polarities of current flow at
typically 30 mA.
Pin 8 – VEE
The circuit is designed to work in either single or dual
power supply applications. Pin 8 is always connected to the
most negative supply.
Pin 9 – Digital Output
The digital output provides the results of the delta
modulator’s conversion. It swings between VCC and VEE and
is CMOS or TTL compatible. Pin 9 is inverting with respect to
Pin 1 and noninverting with respect to Pin 2. It is clocked on
the falling edge of Pin 14. The typical 10% to 90% rise and fall
times are 250 ns and 50 ns respectively for VCC = 12 V and
CL = 25 pF to ground.
Pin 10 – VCC/2 Output
An internal low impedance mid–supply reference is
provided for use in single supply applications. The internal
regulator is a current source and must be loaded with a
resistor to ensure its sinking capability. If a +6.0 dBmo signal
is expected across a 600
input bias resistor, then Pin 10
must sink 2.2 V/600
= 3.66 mA. This is possible only if
Pin 10 sources 3.66 mA into a resistor normally and will
source the difference under peak load. The reference load
resistor is chosen accordingly. A 0.1
μ
F bypass capacitor
from Pin 10 to VEE is also recommended. The VCC/2
reference is capable of sourcing 10 mA and can be used as
a reference elsewhere in the system circuitry.
Pin 11 – Coincidence Output
The coincidence output will be low whenever the content
of the internal 3–bit shift register is all 1s or all 0s. Pin 11 is
an open collector NPN device and requires a pull–up
resistor. If the syllabic filter is to have equal charge and
discharge time constants, the value of RP should be much
less than RS. In systems requiring different charge and
discharge constants, the charging constant is RSCS while
the decay constant is (RS + RP)CS. Thus, longer decays are
easily achievable. The NPN device should not be required to
sink more than 3.0 mA. The typical 10% to 90% rise and fall
times are 200 ns and 100 ns respectively for RL = 4.0 k
to
12 V and CL = 25 pF to ground.
Pin 12 – Digital Threshold
This input sets the switching threshold for Pins 13, 14 and
15. It is intended to aid in interfacing different logic families
without external parts. Typically it is connected to the VCC/2
reference for CMOS interface or can be biased two diode
drops above VEE for TTL interface.
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