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參數(shù)資料
型號: MC44725VFU
廠商: Motorola, Inc.
英文描述: Digital Video Encoder
中文描述: 數(shù)字視頻編碼器
文件頁數(shù): 26/39頁
文件大小: 518K
代理商: MC44725VFU
MC44724/5 Rev 0.21 03/25/97
No.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
Sub-address 71 : Sync control (write/read)
MSB
LSB
Register 71
non-inter
VBI SW
h-polarity v-polarity
default : 0000_0100(bin)
f-polarity h- delay2 h-delay1
h-delay0
non-inter
: non-interlaced mode select
0 : interlace mode (default)
1 : non-interlace mode
VBI SW
: vertical blanking information signal input control switch on EXT pin
0 : VBI input Off (default)
1 : VBI input On
h-polarity
: polarity of Hsync
0 : negative (default)
1 : positive
v-polarity
: polarity of Vsync
0 : negative (default)
1 : positive
f-polarity
: polarity of Fsync
0 : field1 (odd) = low level (default)
1 : field1 (odd) = high level
h-delay2
h-delay1
h-delay0
: delay on Hsync with referance to DVIN data in Master mode
000: + 4 clock delay
001: + 3 clock delay
010: + 2 clock delay
011: + 1 clock delay
100: + 0 clock delay
101: - 1 clock delay
110: - 2 clock delay
111: - 3 clock delay
Note : this h-delay can be also related with 7A[7:0] register and can
delay totally +2023 clock delay in H/V or H/Fsynnc slave mode.
26
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