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參數資料

MC44724/5 Rev 0.21 03/25/97

No.

This document contains information on a new product. Specifications and information herein are subject to change without notice.

Sub-address 7B : Digital Video Input Select Control (write only)

MSB

LSB

Cr _tmg 2

Cr_tmg1

default : 0000_0000(bin)

Y_tmg

Cr/Cb_tmg2

Cr/Cb_tmg1

: Cr/Cb clock timing delay in 16-bit Digital Input Mode

00 : Cr clock delay 0 clock (default)

01 : Cr clock delay +1 clock

10 : Cr clock delay +2 clock

11 : Cr clock delay +3 clock

Y_tmg

: Y clock timing delay in 16-bit Digital Input Mode

0 : Y clock delay 0 clock (default)

1 : Y clock delay +1 clock

16-bit

input mode

: 16-bit Multiplexed CbYCrY Digital Video Input mode

0 : 8-bit CbYCrY Digital Video Input mode (default)

1 : 16-bit CbYCrY Digital Video Input mode

16-bit

input mode

Cb _tmg 2

Cb_tmg1

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