
Applications Information
MOTOROLA
MC68030 USER’S MANUAL
12-21
The structure of this design is very similiar to the previous design and can similarly be
divided into three main sections:
1. The byte select and address decode section (provided by the PAL).
2. The actual memory section (SRAMs).
3. The buffer/latch section (address and data).
The same PAL equations listed in Figure 12-10 are used with the exception of the TERM
signal. Figure 12-13 shows the equation for TERM, which is used by the two clock read and
write design.
TERM = /A16 * /A17 * /A16 * A30 ;immediate STERM for both reads and writes
Figure 12-13. Example PAL Equation for Two-Clock Read and Write
Memory Bank
TERM is simply an address decode signal in this design because both read and write
operations complete in two clock periods. The other signals generated by the PAL have
already been discussed in the previous design and are not repeated here. A latched version
of AS is generated by a 74F74 D-type flip-flop and used to qualify the individual byte select
signals from the PAL. The required SRAM data setup time on write cycles is ensured by
keeping the write strobes (W) active to the SRAMs until the rising edge of the clock that
completes the MC68030 write operation.
The memory section in this design uses 25-ns SRAMs rather than the 35-ns SRAMs used
in the previous design. The faster SRAMs compensate for the 74F373 transparent latches
used on the address lines. Since the memory write operations complete after the MC68030
write bus cycle, both address and data are latched and held valid to the SRAMs until the
write strobes (W) negate. During read operations, the transparent latches on the address
lines remain in the transparent mode, allowing the SRAMs to provide data through the
74F244 buffers in time to meet the specified data setup time to the MC68030.
Figure 12-12. Example Two-Clock Read and Write Memory Bank
CLK
REFILL
STATUS
INSTRUCTION
BOUNDARIES
FIG 12-12
PENDING TRACE OR
INTERRUPT EXCEPTION
PROCESSING