
Index
MOTOROLA
MC68030 USER’S MANUAL
Index-15
Restore Operation 11-51
Save Operation 11-51
Shift/Rotate Instruction 11-45
Single Operand Instruction 11-44
Table Search 11-51
Trace Exception 8-12, 10-70
Signals 12-38
Tradeoffs, Performance 11-1
Transfer
Long Word to Long Word, Misaligned
Cachable 7-19
Long Word to Word 7-10
Misaligned
Cachable Word to Long Word 7-15
Cachable Word to Word 7-15
Long Word to Long Word 7-19
Long Word to Word 7-15
Word to Word 7-15
Word to Word, Timing 7-15
Word to Byte 7-13
Transfer Main Processor Control Register
Primitive 10-50, 10-52
Transfer Multiple Coprocessor Registers
Primitive 10-52
Transfer Multiple Main Processor Registers
Primitive 10-52
Transfer Operation Word Primitive 10-40
Transfer Single Main Processor Register
Primitive 10-50, 10-52
Transfer Size Signals 5-4, 7-4, 7-8–7-9, 7-22
Transfer Status Register and ScanPC
Primitive 10-55
Transfer to/from Top of Stack Primitive 10-49
Translation Control Register 1-9, 2-5, 9-8,
9-54
Translation Table Descriptors 9-10, 9-20
Translation Table Tree 9-5–9-6, 9-11, 9-28,
9-47–9-48, 9-65
Translation Tree, Supervisor 9-48
Protection Example 9-50
Translation, Address 9-13
Transparent Translation Registers 1-9, 2-5,
9-16, 9-57
Tree, Translation Table 9-5–9-6, 9-11, 9-28,
9-47–9-48, 9-65
TT0 1-9, 2-5, 9-16, 9-57
TT1 1-9, 2-5, 9-16, 9-57
Two Clock Synchronous Static RAM 12-18
Types
Address Space 4-5
Data 1-10
U
Unimplemented Instruction Exception 8-9
Unit
Execution 6-16
Memory Management 1-15, 7-3,
7-37–7-38, 7-43, 9-1, 11-6, 12-5
Units, Floating Point 12-5
Unused Descriptor Bits 9-71
User Privilege Level 4-2, 4-4
User Program Stack 2-38
V
Valid Format Word 10-24
Vallocate Routine 9-78
VBR 1-8, 2-5
V
CC
Pin Assignments 12-46
Vector
Base Register 1-8, 2-5
Numbers, Exception 8-1
Vectors, Exception 4-6
Virtual Machine 1-12
Virtual Memory 1-12, 9-77
W
WA Bit 6-21
Wait States 11-18
Window
Asynchronous Sample 7-3
Word Read Cycle, Asynchronous, 32-Bit Port
Timing 7-31
Word to Byte Transfer 7-13
Word to Long-Word Transfer, Misaligned
7-15
Word to Word Transfer, Misaligned Cachable
7-15
Word Write Cycle, Asynchronous, 32-Bit Port
Timing 7-37
Word Write Timing 7-13
Word, Special Status 8-28
Write Allocate Bit 6-21
Write Cycle
Asynchronous 7-37