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參數資料
| 型號： | MC68160FB |
| 廠商： | MOTOROLA INC |
| 元件分類： | 網絡接口 |
| 英文描述： | ENHANCED ETHERNET INTERFACE TRANSCEIVER |
| 中文描述： | DATACOM, ETHERNET TRANSCEIVER, PQFP52 |
| 封裝： | PLASTIC, TQFP-52 |
| 文件頁數： | 6/30頁 |
| 文件大小： | 372K |
| 代理商： | MC68160FB |
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MC68160 MC68160B MC68160C
Table 1. Pin Function Description (continued)
6
MOTOROLA ANALOG IC DEVICE DATA
Pin(s)
Symbol
Type
Name/Function
STATUS INDICATOR
40
TXLED
O
TTL/CMOS
Transmit Status LED Driver Output:
This pin indicates the transmit status of the currently
selected TP or AUI port. When there is no transmit activity detected, an internal pull–up takes
this pin to its normal off (high) state. When transmit activity is detected, the LED driver turns
on. In its on state, TXLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.
41
RXLED
O
TTL/CMOS
Receive Status LED Driver Output:
This pin indicates the receive status of the currently
selected TP or AUI port. When there is no receive activity detected, an internal pull–up takes
this pin to its normal off (high) state. When receive activity is detected, the LED driver turns
on. In its on state, RXLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.
42
CLLED
O
TTL/CMOS
Collision Status LED Driver Output:
This pin indicates the collision status of the currently
selected TP or AUI port. When there is no collision activity detected, an internal pull–up takes
this pin to its normal off (high) state. When collision activity is detected, the LED driver turns
on. In its on state, CLLED flashes the LED by driving low at approximately 10 Hz at a 50%
duty cycle. In the standby mode, this output is driven to the high impedance state.
43
TPLIL
O
TTL/CMOS
Twisted Pair Link Integrity Output:
This output is driven to the low output state to indicate
good link integrity on the TP port during TP mode. It is deasserted (high) when link integrity
fails in TP mode. The TPLIL output is driven to the high impedance state when the AUI port
is selected. In the standby mode, this output is also driven to the high impedance state.
44
TPPLR
O
TTL/CMOS
Twisted Pair Polarity Error Output:
If TPAPCE is high and the wires connected to the
Twisted Pair Receiver Inputs (TPRX+, TPRX–) are reversed, TPPLR will be driven to the low
logic state to indicate the fault. TPPLR remains low when the MC68160, B and C has
automatically corrected for the reversed wires. If the twisted pair link integrity tests fail, this
output will be driven to the high logic state. When the AUI mode is selected this output is
driven to the high impedance state. In the standby mode, this output is also driven to the high
impedance state.
45
TPJABB
O
TTL/CMOS
Twisted Pair Jabber Output:
This pin is driven high to indicate a jabber condition at the
TPTX+/– outputs. (Jabber condition also causes CLLED to be driven alternately to the high
and low output levels). TPJABB is driven to the low output state when no jabber condition is
present. When the AUI mode is selected this output is driven to the high impedance state. In
the standby mode, this output is also driven to the high impedance state.
POWER SUPPLY AND GROUND
10
VDDDIV
Frequency Divider Supply Pin
11
13
VDDFM
GNDFM
Frequency Multiplier Supply and Ground Pins
14
15
GNDVCO
VDDVCO
Voltage Controlled Oscillator Ground and Supply Pins
20
GNDSUB
Substrate Ground Pin
7
8
18
19
VDDDIG
GNDDIG
VDDDIG
GNDDIG
Digital Supply and Ground Pins
30
33
VDDANA
GNDANA
Analog Supply and Ground Pins
34
35
38
39
GNDPWR
VDDPWR
VDDPWR
GNDPWR
Power Supply and Ground Pins
47
GNDCTL
Controller Interface Ground Pin
NOTE
:
Power and ground pins are not connected internally. Failure to connect externally may cause malfunction or damage to the IC.
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