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| 型號(hào)： | MC68341 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Integrated Processor Users Manual |
| 中文描述： | 綜合處理器用戶(hù)手冊(cè) |
| 文件頁(yè)數(shù)： | 18/21頁(yè) |
| 文件大小： | 134K |
| 代理商： | MC68341 |
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MOTOROLA
MC68341 USER’S MANUAL ADDENDUM
17
edges of the clock signals - the PLL phase locks the falling edge of CLKOUT to the falling edge on EXTCLK.
70. Data Setup Time for 3.3V
On page 12-9, electrical specification #27 (Data Setup to CLKOUT Low) for 3.3V product only has been
changed from 5ns to 8ns.
71. UWE and LWE Signals
In Figure 12-3 on page 12-12, UWE and LWE will assert for the write buys cycle with the same timing as DS.
In the fast termination write cycle in Figure 12-5 on page 12-14, UWE and LWE (not shown) remain negated
like DS.
72. Serial Module Specs
Note 1 on page 12-25 should reference synchronous operation, not asynchronous.
73. Ordering Information
Replace the the ordering information table in Section 11 with the following ordering information.
74. Upper and Lower Data Strobes
In paragraph 3.2.8 page 3-6, change (D15–D0) to (D15–D8) and (D8–D0) to (D7–D0).
75. Figure 3-2
Change Note 1 to reference MC68341 instead of MC68340.
76. Figure 4-8
The Periodic Interrupt Control Register (PICR) and Periodic Interrupt Timing Register (PITR) should be 1 word
instead of 2 bytes. Disregard the Scale Select Register.
77. Page 4-24
Refer to 4-17 for more information on the AVEC-Automatic Vector Responsibility.
78. Page 4-48
The lake at the start of the code should be INIT341 instead of INIT340.
Supply
Voltage
Package Type
Frequency
(MHz)
Temperature
Order Number
5.0 V
Plastic Quad Flat Pack
FT Suffix
Plastic Quad Flat Pack
FT Suffix
Plastic Quad Flat Pack
FT Suffix
0 – 25
0
-40
0
°
-40
0
°
°
C to +70
°
to 85
C to +70
°
to 85
C to +70
°
C
°
C
°
C
°
C
C
°
XC68341FT25
XC68341CFT25
XC68341FT16
XC68341CFT16
XC68341FT16V
5.0 V
0 – 16.78
3.3 V
0 – 16.78
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