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參數資料
| 型號： | MC68360UMAD |
| 廠商： | Motorola, Inc. |
| 英文描述： | Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1 |
| 中文描述： | 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1 |
| 文件頁數： | 17/28頁 |
| 文件大?。?/td> | 159K |
| 代理商： | MC68360UMAD |
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MOTOROLA
MC68360 USER’S MANUAL ERRATA
17
In MC68040 companion mode, the QUICC understands
MC68040-type bus cycles but cannot generate them. If the
QUICC becomes busmaster, e. g. for SDMA transfers, it will
drive normal MC68030-type bus cycles with TT1 becoming DS
again. This should normally be no problem since the MC68040
does not interpret these input signals, but external circuitry han-
dling these signals must be aware of this fact.
6. Error in Figure 9-8.
On page 9-33, Figure 9-8, the buffer between RESETH, RSTI, the pushbutton and
CONFIG2 should not have an inverting output; it should be a non-inverting buffer.
7. Error in Reset Strategy.
On Page 9-34, section 9.4.1.3, the first sentence “If a QUICC is configured to provide the
global chip select, it will also provide an internal power-on reset generation.” is not correct.
QUICC will provide internal power-on reset generation regardless of chip select
configuration.
8. Error in Caching Sample Code.
On Page 9-53, section 9.5.4, correct the following in the code sample:
a) ‘MOVE.L #$003FC020,D0’ should be changed to ‘MOVE.L #$003FC040,D0’.
b) ‘MOVE.L #$403FC010,D0’ should be changed to ‘MOVE.L #$403FC020,D0’.
9. Error in Figure 9-33. 1-Mbyte DRAM Bank—32 Bits Wide.
On Page 9-87, Figure 9-33, correct the following:
a) On the first MC74F157, B0-B3 should be connected to A11-A14, not A12-A15.
b) On the second MC74F157, B0-B3 should be connected to A15-A18, not A16-A19.
c) On the third MC74F157, A1 and B1 should be unused (unconnected).
d) On the third MC74F157, B0 should be connected to A19, not A20.
e) On the third MC74F157, Y1-Y3 should be unused (unconnected).
Section 10 – Electrical Characteristics
1. Missing Note on Maximum Ratings
On Page 10-1, the following note should be added to the maximum ratings figure:
3. The supply voltage V
cc
must start and restart from 0.0 V; otherwise, the 360 will not come
out of reset properly.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68360VR25L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25LR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25VL | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25VLR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR33L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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