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參數資料
| 型號： | MC68360UMAD |
| 廠商： | Motorola, Inc. |
| 英文描述： | Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1 |
| 中文描述： | 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1 |
| 文件頁數： | 3/28頁 |
| 文件大小： | 159K |
| 代理商： | MC68360UMAD |
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MOTOROLA
MC68360 USER’S MANUAL ERRATA
3
are not correct, the correct text is below.
“The equations of the byte write enables for 32-bit port (DPS/SPS set to 32 bit) are as
follows:”
“The equations of the byte write enables for 16-bit port (DPS/SPS set to 16 bit) are as
follows:”
Also in the same section the first sentence of the note:
“Note that the WE signals are not affected by dynamic bus sizing.” is not correct and should
be removed.
2. Error in slave mode bus arbitration diagram.
On page 4-56, figure 4-38 an arrow head and text was missing.
The line top line between “QUICC waiting for bus, BR asserted” and “IDLE” state should
have an arrow head facing the IDLE state.
Also on the same figure, the Idle state should have a test of “BG Negated” under the text of
“BR Negated”.
3. Power on reset operation
On page 4-65, the note “User should make sure the ramp up time of Vcc never be faster
than 4mSec to ensure proper power on reset sequence. “This restriction has been removed
and the note should be deleted.
NOTE for Rev C.0
Due to a problem with Revision C.0 of the QUICC (masks
0E63C and 0F15W), a 4ms minimum Vcc ramp-up specification
was added. Characterization of Revision C.1 QUICCs (masks
1E68C and 0E68C) has demonstrated that this specification is
no longer necessary.
Users of Revision C.0 QUICCs should remain aware of this po-
tential problem source. Revision C.0 QUICCs used in systems
with very fast ramp-up times may experience problems at pow-
er-on reset. When the problem occurs, the QUICC never comes
out of reset and no bus activity occurs (similar to latch-up, but
without the high current drain). If the problem occurs, the only
solution is powering the device down and reapplying power (i.e.
another power-on reset).
Hardware reset (RESETH) will not solve the problem.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
n
.
相關PDF資料 |
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|---|---|
| MC68360CFE25 | QUad Integrated Communications Controller Users Manual |
| MC68360CRC25 | QUad Integrated Communications Controller Users Manual |
| MC68360FE25 | QUad Integrated Communications Controller Users Manual |
| MC68360FE25V | QUad Integrated Communications Controller Users Manual |
| MC68360FE33 | QUad Integrated Communications Controller Users Manual |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68360VR25L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25LR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25VL | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25VLR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR33L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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