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參數資料
| 型號： | MC68360UMAD |
| 廠商： | Motorola, Inc. |
| 英文描述： | Errata and Added Information to MC68360 Quad Integrated Communication Controller User Manual Rev 1 |
| 中文描述： | 勘誤表和新增的資料MC68360四綜合通信控制器用戶手冊修訂1 |
| 文件頁數： | 21/28頁 |
| 文件大?。?/td> | 159K |
| 代理商： | MC68360UMAD |
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MOTOROLA
MC68360 USER’S MANUAL ERRATA
21
master QUICC may assert a spurious bus grant. If more than one QUICC slave is used with
a QUICC in master mode the user should not wire-or the bus grant signal to avoid bus
contention due to this spurious bus grant assertion.
15. Missing Minimum Specification.
On page 10-36, Table 10.12, the minimum specification for specification 152 was not
correct. The correct specifications are 20ns for 25MHz and 15ns for 33MHz. On the same
page the maximum specification for specification 161A was missing. The max spec is 23ns
for 33MHz. On the same page the minimum specification for 166 was missing. The minimum
specification should have been 3ns for both 25MHz and 33MHz.
Also on page10-36, at the bottom of the table, note 2 should state:
“2. For internal/external bus master to external memory or peripheral. The max for J17A and
newer masks is 12ns; J17A was released 2Q97.”
16. Typo on Figure 10-31.
On page 10-42, Figure 10-31, specification 187 was referenced to the wrong place. The cor-
rect reference should be from assertion of MBARE to assertion of DS.
17. Typo on specification number.
On page 10-45 and page 10-47 the specification number for R/W to AS assertion should be
214 not 164
18. Typo on External MC68030/MC68360 DRAM Asynchronous Cycle Timing Diagram.
On page 10-47, Figure 10-35, the specification for AMUX signal negation should be 119.
Specification 209 should be replaced with specification 119.
19. The clock reference is EXTAL, not CLKO1.
On pages 10-51 and 10-56, the following note should be added:
3. The clock reference is EXTAL, not CLKO1.
On the same pages, superscript of 3 should be added for specifications 252, 258 and 296.
Also on the same page spec 252 the max value for 33MHz should be 5nSec not 6nSec.
20. Correction on Figure 10-40.
On page 10-52, Figure 10-40, the note under D31–D0 should be “(040 READ)” and
“(OUTPUT)”.
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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相關代理商/技術參數 |
參數描述 |
|---|---|
| MC68360VR25L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25LR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25VL | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR25VLR2 | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
| MC68360VR33L | 功能描述:微處理器 - MPU QUICC SIM 4SCC RoHS:否 制造商:Atmel 處理器系列:SAMA5D31 核心:ARM Cortex A5 數據總線寬度:32 bit 最大時鐘頻率:536 MHz 程序存儲器大小:32 KB 數據 RAM 大小:128 KB 接口類型:CAN, Ethernet, LIN, SPI,TWI, UART, USB 工作電源電壓:1.8 V to 3.3 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-324 |
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