
CPU32+
5-70
MC68360 USER’S MANUAL
MOTOROLA
Figure 5-27. Command Sequence Diagram
Table 5-23. BDM Command Summary
Command
Mnemonic
RAREG/RDREGrial interface.
WAREG/WDREG The data operand is written to the specified address or data register.
The specified system control register is read. All registers that can be read
in supervisor mode can be read in BDM.
WSREG
The operand data is written into the specified system control register.
Read the sized data at the memory location specified by the long-word ad-
dress. The SFC register determines the address space accessed.
Write the operand data to the memory location specified by the long-word
address. The DFC register determines the address space accessed.
Used in conjunction with the READ command to dump large blocks of mem-
ory. An initial READ is executed to set up the starting address of the block
and to retrieve the first result. Subsequent operands are retrieved with the
DUMP command.
Used in conjunction with the WRITE command to fill large blocks of memory.
An initial WRITE is executed to set up the starting address of the block and
to supply the first operand. Subsequent operands are written with the FILL
command.
The pipeline is flushed and refilled before resuming instruction execution at
the return PC.
Current PC is stacked at the location of the current SP. Instruction execution
begins at user patch code.
Asserts RESET for 512 clock cycles. The CPU is not reset by this command.
Synonymous with the CPU RESET instruction.
NOP
NOP performs no operation and may be used as a null command.
Description
Read A/D Register
Write A/D Register
Read System Register
Write System Register
Read Memory Location
READ
Write Memory Location
WRITE
Dump Memory Block
DUMP
Fill Memory Block
FILL
Resume Execution
GO
Call User Code
CALL
Reset Peripherals
RST
No Operation
COMMANDS TRANSMITTED TO THE CPU32
COMMAND CODE TRANSMITTED DURING THIS CYCLE
HIGH-ORDER 16 BITS OF MEMORY ADDRESS
LOW-ORDER 16 BITS OF MEMORY ADDRESS
SEQUENCE TAKEN IF
OPERATION HAS NOT
COMPLETED
DATA UNUSED FROM
THIS TRANSFER
SEQUENCE TAKEN IF
ILLEGAL COMMAND
IS RECEIVED BY CPU32
RESULTS FROMPREVIOUS COMMAND
RESPONSES FROMTHE CPU
NONSERIAL-RELATED ACTIVITY
MS ADDR
"NOT READY"
XXX
"ILLEGAL"
LS ADDR
"NOT READY"
NEXT CMD
"NOT READY"
READ (LONG)
NEXT CMD
"NOT READY"
XXX
"NOT READY"
XXX
XXX
BERR/AERR
MS RESULT
NEXT CMD
LS RESULT
READ
MEMORY
LOCATION
NEXT
COMMAND
CODE
SEQUENCE TAKEN IF BUS ERROR
OR ADDRESS ERROR OCCURS ON
MEMORY ACCESS
HIGH- AND LOW-ORDER
16 BITS OF RESULT