
Signal Descriptions
MOTOROLA
MC68360 USER’S MANUAL
2-9
2.1.7.7 OUTPUT ENABLE/ADDRESS MULTIPLEX (OE/AMUX).
grammed as the output enable (OE) output or as the address multiplex output.
This pin can be pro-
OE—During a read cycle, this output signal is driven by the bus master to indicate that an
external device should place valid data on the data bus. OE may used to save an external
inversion of the R/W signal.
AMUX—This output signal is driven by the DRAM controller to the external address multi-
plexer. AMUX need not be used if the DRAM addresses are multiplexed internally by the
QUICC.
2.1.7.8 BYTE WRITE ENABLE (WE3–WE0)
description.
.
See 2.1.1.2 Address Bus (A31–A28) for the
2.1.8 Bus Arbitration Signals
The following signals are the four bus arbitration control signals used to determine the bus
master. Refer to Section 4 Bus Operation for more information concerning these signals.
2.1.8.1 BUS REQUEST (BR).
needs to become the bus master. This input is typically wire-ORed.
This active-low input signal indicates that an external device
2.1.8.2 BUS GRANT (BG).
master has relinquished the bus.
Assertion of this active-low output signal indicates that the bus
2.1.8.3 BUS GRANT ACKNOWLEDGE (BGACK).
cates that an external device has become the bus master.
Assertion of this active-low input indi-
2.1.8.4 READ-MODIFY-WRITE CYCLE/INITIAL CONFIGURATION (RMC/CONFIG0).
This pin can be programmed as the read-modify-write cycle output or as the initial configu-
ration pin 0 input signal during system reset.
RMC—This output signal identifies the bus cycle as part of an indivisible read-modify-write
operation; it remains asserted during all bus cycles of the read-modify-write operation to
indicate that bus ownership cannot be transferred.
NOTE
RMC is muxed with a CONFIG0 pin. RMC only functions when
the CPU32+ is enabled, and is an output unless an external
master ownes the bus, in which case it is an input.
CONFIG0—See 2.1.13 Initial Configuration Pins (CONFIG) for the description.
2.1.8.5 BUS CLEAR OUT/INITIAL CONFIGURATION/ROW ADDRESS SELECT
DOUBLE-DRIVE (BCLRO/CONFIG1/RAS2DD).
clear out output or as the initial configuration pin 1 input signal during system reset or as the
RAS2DD output double-drive signal.
This pin can be programmed as the bus