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參數資料
| 型號： | MC68HC11A8BVP2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HCMOS Single-Chip Microcontroller |
| 中文描述： | 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48 |
| 封裝： | DIP-48 |
| 文件頁數： | 30/158頁 |
| 文件大小： | 776K |
| 代理商： | MC68HC11A8BVP2 |
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MOTOROLA
3-4
ON-CHIP MEMORY
MC68HC11A8
TECHNICAL DATA
3
In expanded multiplexed operating modes, memory locations are basically the same
as the single- chip operating modes; however, the locations between the shaded ar-
eas (designated EXT) are for externally addressed memory and l/O. If an external
memory or l/O device is located to overlap an enabled internal resource, the internal
resource will take priority. For reads of such an address the data (if any) driving the
port C data inputs is ignored and will not result in any harmful conflict with the internal
read. For writes to such an address data is driven out of the port C data pins as well
as to the internal location. No external devices should drive port C during write access-
es to internal locations; however, there is normally no conflict since the external ad-
dress decode and/ or data direction control should incorporate the R/W signal in their
development. The R/W, AS, address, and write data signals are valid for all accesses
including accesses to internal memory and registers.
The special bootstrap operating mode memory locations are similar to the single-chip
operating mode memory locations except that a bootstrap program at memory loca-
tions $BF40 through $BFFF is enabled. The reset and interrupt vectors are addressed
at $BFC0–$BFFF while in the special bootstrap operating mode. These vector ad-
dresses are within the 192 byte memory used for the bootstrap program.
The special test operating mode memory map is the same as the expanded multi-
plexed operating mode memory map except that the reset and interrupt vectors are
located at external memory locations $BFC0–$BFFF.
3.2 RAM and I/O Mapping Register (INIT)
There are 64 internal registers which are used to control the operation of the MCU.
These registers can be relocated on 4K boundaries within the memory space, using
the INIT register. Refer to
Table 3-1
for a complete list of the registers. The registers
and control bits are explained throughout this document.
The INIT register is a special-purpose 8-bit register which may be used during initial-
ization to change the default locations of RAM and control registers within the MCU
memory map. It may be written to only once within the initial 64 E clock cycles after a
reset and thereafter becomes a read-only register.
The default starting address for internal RAM is $0000 and the default starting address
for the 64 control registers is $1000 (the INIT register is set to $01 at reset). The upper
four bits of the INIT register specify the starting address for the 256 byte RAM and the
lower four bits of INIT specify the starting address for the 64 control registers. These
four bits are matched to the upper four bits of the 16-bit address.
Throughout this document, the control register addresses will be displayed with the
high-order digit shown as a bold “
1
” to indicate that the register block may be relocated
to some 4K memory page other than its default position of $1000-$103F.
7
6
5
4
3
2
1
0
$
1
03D
RESET
RAM3
0
RAM2
0
RAM1
0
RAM0
0
REG3
0
REG2
0
REG1
0
REG0
1
INIT
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相關代理商/技術參數 |
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