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參數資料
型號: MC68HC11A8BVP2
廠商: MOTOROLA INC
元件分類: 微控制器/微處理器
英文描述: HCMOS Single-Chip Microcontroller
中文描述: 8-BIT, MROM, 2 MHz, MICROCONTROLLER, PDIP48
封裝: DIP-48
文件頁數: 65/158頁
文件大小: 776K
代理商: MC68HC11A8BVP2
MC68HC11A8
TECHNICAL DATA
ANALOG-TO-DIGITAL CONVERTER
MOTOROLA
7-1
7
7 ANALOG-TO-DIGITAL CONVERTER
The MC68HC11A8 includes an 8-channel, multiplexed-input, successive approxima-
tion, analog-to-digital (A/D) converter with sample and hold to minimize conversion er-
rors caused by rapidly changing input signals. Two dedicated lines (V
RL
, V
RH
) are
provided for the reference voltage inputs. These pins may be connected to a separate
or isolated power supply to ensure full accuracy of the A/D conversion. The 8-bit A/D
converter has a total error of
±
1 LSB which includes
±
1/2 LSB of quantization error
and accepts analog inputs which range from V
RL
to V
RH
. Smaller analog input ranges
can also be obtained by adjusting V
RH
and V
RL
to the desired upper and lower limits.
Conversion is specified and tested for V
RL
= 0 V and V
RH
= 5 V
±
10%; however, lab-
oratory characterization over the full temperature range indicates little or no degrada-
tion with V
RH
-V
RL
as low as 2.5 to 3 V. The A/D system can be operated with V
RH
below
V
DD
and/or V
RL
above V
SS
as long as V
RH
is above V
RL
by enough to support the con-
versions (2.5 to 5.0 V). Each conversion is accomplished in 32 MCU E clock cycles,
provided the E clock rate is greater than 750 kHz. For systems which operate at clock
rates less than 750 kHz, an internal R-C oscillator must be used to clock the A/D sys-
tem. The internal R-C oscillator is selected by setting the CSEL bit in the OPTION reg-
ister.
NOTE
Only four A/D input channels are available in the 48-pin version.
7.1 Conversion Process
The A/D converter is ratiometric. An input voltage equal to V
RL
converts to $00 and an
input voltage equal to V
RH
converts to $FF (full scale), with no overflow indication. For
ratiometric conversions, the source of each analog input should use V
RH
as the supply
voltage and be referenced to V
RL
.
Figure 7-1
shows the detailed sequence for a set of four conversions. This sequence
begins one E clock cycle after a write to the A/D control/status register (ADCTL).
Fig-
ure 7-2
shows a model of the port E A/D channel inputs. This model is useful for un-
derstanding the effects of external circuitry on the accuracy of A/D conversions.
7.2 Channel Assignments
A multiplexer allows the single A/D converter to select one of sixteen analog signals.
Eight of these channels correspond to port E input lines to the MCU, four of the chan-
nels are for internal reference points or test functions, and four channels are reserved
for future use.
Table 7-1
shows the signals selected by the four channel select control
bits.
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