
MC68HC11KW1
MOTOROLA
4-5
OPERATING MODES AND ON-CHIP MEMORY
4
Table 4-2
Register and control bit assignments (Page 1 of 5)
Register name
Address
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
State
on reset
Port A data (PORTA)
$0000
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
undefined
Data direction A (DDRA)
$0001
DDA7 DDA6 DDA5 DDA4 DDA3 DDA2 DDA1 DDA0 0000 0000
Data direction B (DDRB)
$0002
DDB7 DDB6 DDB5 DDB4 DDB3 DDB2 DDB1 DDB0 0000 0000
Data direction F (DDRF)
$0003
DDF7 DDF6 DDF5 DDF4 DDF3 DDF2 DDF1 DDF0 0000 0000
Port B data (PORTB)
$0004
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
undefined
Port F data (PORTF)
$0005
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
undefined
Port C data (PORTC)
$0006
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
undefined
Data direction C (DDRC)
$0007
DDC7 DDC6 DDC5 DDC4 DDC3 DDC2 DDC1 DDC0 0000 0000
Port D data (PORTD)
$0008
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
undefined
Data direction D (DDRD)
$0009
DDD7 DDD6 DDD5 DDD4 DDD3 DDD2 DDD1 DDD0 0000 0000
Port E data (PORTE)
$000A
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
undefined
Timer compare force (CFORC)
$000B
FOC1 FOC2 FOC3 FOC4 FOC5
0
0
0
0000 0000
Output compare 1 mask (OC1M)
$000C OC1M7OC1M6OC1M5OC1M4OC1M3
0
0
0
0000 0000
Output compare 1 data (OC1D)
$000D OC1D7 OC1D6 OC1D5 OC1D4 OC1D3
0
0
0
0000 0000
Timer count (TCNT) high
$000E
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 0000 0000
Timer count (TCNT) low
$000F
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 0000 0000
Timer input capture 1 (TIC1) high
$0010
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
undefined
Timer input capture 1 (TIC1) low
$0011
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
Timer input capture 2 (TIC2) high
$0012
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
undefined
Timer input capture 2 (TIC2) low
$0013
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
Timer input capture 3 (TIC3) high
$0014
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8)
undefined
Timer input capture 3 (TIC3) low
$0015
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0)
undefined
Timer output compare 1 (TOC1) high $0016
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer output compare 1 (TOC1) low
$0017
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Timer output compare 2 (TOC2) high $0018
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer output compare 2 (TOC2) low
$0019
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Timer output compare 3 (TOC3) high $001A
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer output compare 3 (TOC3) low
$001B
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Timer output compare 4 (TOC4) high $001C
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Timer output compare 4 (TOC4) low
$001D
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Capture 4/compare 5 (TI4/O5) high
$001E
(bit 15)
(14)
(13)
(12)
(11)
(10)
(9)
(bit 8) 1111 1111
Capture 4/compare 5 (TI4/O5) low
$001F
(bit 7)
(6)
(5)
(4)
(3)
(2)
(1)
(bit 0) 1111 1111
Timer control 1 (TCTL1)
$0020
OM2
OL2
OM3
OL3
OM4
OL4
OM5
OL5
0000 0000
Timer control 2 (TCTL2)
$0021 EDG4BEDG4AEDG1BEDG1AEDG2BEDG2AEDG3BEDG3A 0000 0000
Timer interrupt mask 1 (TMSK1)
$0022
OC1I
OC2I
OC3I
OC4I
I4/O5I
IC1I
IC2I
IC3I
0000 0000
TPG
47