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參數資料
型號： MC68HCL05C9A
廠商： Motorola, Inc.
元件分類： 8位微控制器
英文描述： 8-Bit Microcontroller(8位微控制器)
中文描述： 8位微控制器（8位微控制器）
文件頁數： 73/160頁
文件大小： 783K
代理商： MC68HCL05C9A
Serial Communications Interface (SCI)
Functional Description
MC68HC05C9A
—
Rev. 4.0
General Release Specification
MOTOROLA
Serial Communications Interface (SCI)
73
L
G
R
interrupts are enabled). The transfer of data to the transmit data shift
register is synchronized with the bit rate clock (see
Figure 9-2
). All data
is transmitted least significant bit first. Upon completion of data
transmission, the transmission complete flag (TC) in the SCSR is set
(provided no pending data, preamble, or break is to be sent) and an
interrupt is generated (if the transmit complete interrupt is enabled). If
the transmitter is disabled, and the data, preamble, or break (in the
transmit data shift register) has been sent, the TC bit will be set also.
This will also generate an interrupt if the transmission complete interrupt
enable bit (TCIE) is set. If the transmitter is disabled during a
transmission, the character being transmitted will be completed before
the transmitter gives up control of the TDO pin.
When SCDR is read, it contains the last data byte received, provided
that the receiver is enabled. The receive data register full flag bit (RDRF)
in the SCSR is set to indicate that a data byte has been transferred from
the input serial shift register to the SCDR; this will cause an interrupt if
the receiver interrupt is enabled. The data transfer from the input serial
shift register to the SCDR is synchronized by the receiver bit rate clock.
The OR (overrun), NF (noise), or FE (framing) error flags in the SCSR
may be set if data reception errors occurred.
An idle line interrupt is generated if the idle line interrupt is enabled and
the IDLE bit (which detects idle line transmission) in SCSR is set. This
allows a receiver that is not in the wakeup mode to detect the end of a
message, or the preamble of a new message, or to re-synchronize with
the transmitter. A valid character must be received before the idle line
condition or the IDLE bit will not be set and idle line interrupt will not be
generated.
Figure 9-2. Rate Generator Division
OSC FREQ
(f
OSC
)
÷
2
BUS FREQ
(f
OP
)
SCP0–SCP1
SCI PRESCALER
SELECT
CONTROL
N
SCR0–SCR2
SCI RATE
SELECT
CONTROL
M
÷
16
SCI TRANS
CLOCK (TX)
SCI RECEIVE
CLOCK (RT)
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相關代理商/技術參數
參數描述
MC68HCP11A1CFN3 功能描述:8位微控制器 -MCU 8-bit HCMOS single chip MCU RoHS:否 制造商:Silicon Labs 核心:8051 處理器系列:C8051F39x 數據總線寬度:8 bit 最大時鐘頻率:50 MHz 程序存儲器大小:16 KB 數據 RAM 大小:1 KB 片上 ADC:Yes 工作電源電壓:1.8 V to 3.6 V 工作溫度范圍:- 40 C to + 105 C 封裝 / 箱體:QFN-20 安裝風格:SMD/SMT
MC68HCP11A1FN 制造商:MOTORALA 功能描述:
MC68HCP11E0CP2 制造商:Rochester Electronics LLC 功能描述:- Bulk
MC68HCP11E0FN 功能描述:MICROCONTROLLER MCU 8ADC 3MHC RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:HC11 標準包裝:250 系列:56F8xxx 核心處理器:56800E 芯體尺寸:16-位 速度:60MHz 連通性:CAN，SCI，SPI 外圍設備:POR，PWM，溫度傳感器，WDT 輸入/輸出數:21 程序存儲器容量:40KB（20K x 16） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:6K x 16 電壓 - 電源 (Vcc/Vdd):2.25 V ~ 3.6 V 數據轉換器:A/D 6x12b 振蕩器型:內部 工作溫度:-40°C ~ 125°C 封裝/外殼:48-LQFP 包裝:托盤 配用:MC56F8323EVME-ND - BOARD EVALUATION MC56F8323
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