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參數資料
| 型號： | MCM20014IBMN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 1/3” Color VGA Digital Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數： | 34/54頁 |
| 文件大小： | 761K |
| 代理商： | MCM20014IBMN |
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MOTOROLA
MCM20014
34
The
Internal Timing Control Register; Table 28
, is used
to define the size of internal timing pulse widths. In de-
fault, both
shs
and
shr
are 6 MCLK
’
s wide. The user is
strongly encouraged to write an 00
h
to this register; thus
making these pulse widths 16 MCLKs wide.
5.5.2 Programmable
“
Window of Interest
”
The WOI is defined by a set of registers that indicate the
upper-left starting point for the window and another set
of registers that define the size of the window. Please
refer to
Figure 6, on page 7
for a pictorial representation
of the WOI within the active pixel array.
The WOI Row Pointer;
wrp
[8:0] (
Table 29
and
Table
30
), and the WOI Column Pointer;
wcp
[9:0] (
Table 31
and
Table 32
), mark the upper-left starting point for the
WOI.
The WOI Row Pointer;
wrp
[8:0], has a range of 0
d
to
511
d
whereas the WOI Column Pointer;
wcp
[9:0] has a
usable range of 0
d
to 703
d
. The pointer can be placed
anywhere within the active pixel array.
The WOI Row Depth;
wrd
[8:0] (
Table 29
and
Table 30
),
and the WOI Column Depth;
wcd
[9:0] (
Table 31
and
Table 32
), indicate the size of the WOI.
The WOI Row Depth;
wrd
[8:0], has a range of 0
d
to
511
d
whereas the WOI Column Depth;
wcd
[9:0], has a
range of 0
d
to 703
d
.
The user should be careful to create a WOI that con-
tains active pixels only. There is no logic in the sensor
Address
60
h
Internal Timing Control
Default
66
h
msb (7)
6
5
4
3
2
1
lsb (0)
shs[3]
shs[2]
shs[1]
shs[0]
shr[3]
shr[2]
shr[1]
shr[0]
Bit
Number
Function
Description
Reset
State
7 - 4
shs
shs[3:0] = 0000
b
= 16 MCLKs Wide
shs[3:0] = 0001
b
= 1
d
MCLKs Wide
shs[3:0] = 0010
b
= 2
d
MCLKs Wide
|
shs[3:0] = 0110
b
= 6
d
MCLKs Wide
|
shs[3:0] = 1111
b
= 15
d
MCLKs Wide
0110
b
3 - 0
shr
shr[3:0] = 0000
b
= 16 MCLKs Wide
shr[3:0] = 0001
b
= 1
d
MCLKs Wide
shr[3:0] = 0010
b
= 2
d
MCLKs Wide
|
shr[3:0] = 0110
b
= 6
d
MCLKs Wide
|
shr[3:0] = 1111
b
= 15
d
MCLKs Wide
0110
b
Table 28. Internal Timing Control Register
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