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參數(shù)資料
| 型號(hào)： | MCM20014IBMN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 1/3” Color VGA Digital Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數(shù)： | 42/54頁 |
| 文件大小： | 761K |
| 代理商： | MCM20014IBMN |
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MOTOROLA
MCM20014
42
1 = Read transfer, the slave transitions to a slave
transmitter and sends the data to the master
0 = Write transfer, the master transmits data to the
slave
6.4 Acknowledgment
Only the slave with a calling address that matches the
one transmitted by the master will respond by sending
back an acknowledge bit. This is done by pulling the
SDATA line low at the 9th clock (see
Figure 25
). If a
transmitted slave address is acknowledged, successful
slave addressing is said to have been achieved. No two
slaves in the system may have the same address. The
MCM20014 is configured to be a slave only.
6.5 Data Transfer
Once successful slave addressing is achieved, data
transfer can proceed between the master and the se-
lected slave in a direction specified by the R/W bit sent
by the calling master. Note that for the first byte after a
start signal (in
Figure 25
and
Figure 26
), the R/W bit is
always a
“
0
”
designating a write transfer. This is re-
quired since the next data transfer will contain the reg-
ister address to be read or written.
All transfers that come after a calling address cycle are
referred to as data transfers, even if they carry sub-ad-
dress information for the slave device.
Each data byte is 8 bits long. Data may be changed only
while SCLK is low and must be held stable while SCLK
is high as shown in
Figure 25
. There is one clock pulse
on SCLK for each data bit, the MSB being transferred
first.
Each data byte has to be followed by an acknowledge
bit, which is signalled from the receiving device by pull-
ing the SDATA low at the ninth clock. So one complete
data byte transfer needs nine clock pulses. If the slave
receiver does not acknowledge the master, the SDATA
line must be left high by the slave. The master can then
generate a stop signal to abort the data transfer or a
start signal (repeated start) to commence a new calling.
If the master receiver does not acknowledge the slave
transmitter after a byte transmission, it means 'end of
data' to the slave, so the slave releases the SDATA line
for the master to generate STOP or START signal.
6.6 Stop Signal
The master can terminate the communication by gener-
ating a STOP signal to free the bus. However, the mas-
ter may generate a START signal followed by a calling
command without generating a STOP signal first. This
is called a Repeated START. A STOP signal is defined
as a low-to-high transition of SDATA while SCLK is at
logical
“
1
”
(see
Figure 25
).
The master can generate a STOP even if the slave has
generated an acknowledge bit at which point the slave
must release the bus.
6.7 Repeated START Signal
A Repeated START signal is a START signal generated
without first generating a STOP signal to terminate the
communication. This is used by the master to commu-
nicate with another slave or with the same slave in a dif-
ferent mode (transmit/receive mode) without releasing
the bus.
As shown in
Figure 26
, a Repeated START signal is be-
ing used during the read cycle and to redirect the data
transfer from a write cycle (master transmits the register
address to the slave) to a read cycle (slave transmits
the data from the designated register to the slave).
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