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參數資料
| 型號： | MCM20014IBMN |
| 廠商： | MOTOROLA INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 1/3” Color VGA Digital Image Sensor |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, CQCC48 |
| 封裝： | CERAMIC, LCC-48 |
| 文件頁數： | 43/54頁 |
| 文件大小： | 761K |
| 代理商： | MCM20014IBMN |
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MCM20014
MOTOROLA
43
Figure 25. WRITE Cycle using I2C Bus
6.8 I2C Bus Clocking and Synchronization
Open drain outputs are used on the SCLK outputs of all
master and slave devices so that the clock can be syn-
chronized and stretched using wire-AND logic. This
means that the slowest device will keep the bus from
going faster than it is capable of receiving or transmit-
ting data.
After the master has driven SCLK from High to Low, all
the slaves drive SCLK Low for the required period that
is needed by each slave device and then releases the
SCLK bus. If the slave SCLK Low period is greater than
the master SCLK Low period, the resulting SCLK bus
signal Low period is stretched. Therefore, synchronized
clocking occurs since the SCLK is held low by the de-
vice with the longest Low period. Also, this method can
be used by the slaves to slow down the bit rate of a
transfer. The master controls the length of time that the
SCLK line is in the High state. The data on the SDATA
line is valid when the master switches the SCLK line
from a High to a Low.
Slave devices may hold the SCLK low after completion
of one byte transfer (9 bits). In such case, it halts the bus
clock and forces the master clock into wait states until
the slave releases the SCLK line.
6.9 Register Write
Writing the MCM20014 registers is accomplished with
the following I2C transactions (see
Figure 25
):
Master transmits a START
Master transmits the MCM20014 Slave Calling Ad-
dress with
“
WRITE
”
indicated (BYTE=66
h
, 102
d
,
01100110
b
)
MCM20014 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock, if the Call-
ing Address was received
Master transmits the MCM20014 Register Address
MCM20014 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock after re-
ceiving the Register Address
Master transmits the data to be written into the reg-
ister at the previously received Register Address
MCM20014 slave sends acknowledgment by forc-
ing the SDATA Low during the 9th clock after re-
ceiving the data to be written into the Register
Address
Master transmits STOP to end the write cycle
SCLK
1
2
3
4
5
6
7
8
MSB
1
2
3
4
5
6
7
8
MSB
LSB
9
9
1
2
3
4
5
6
7
8
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
9
Ack
Bit
from
Data to write MCM20014 Register
Stop
Signal
MCM20014
SCLK
SDATA
SDATA
Start
Signal
Ack
Bit
from
AD7 AD6 AD5 AD4 AD3 AD2 AD1
“
0
”
“
1
”
“
0
”
“
1
”
D7
D6 D5
D4 D3 D2 D1 D0
MCM20014 I
2
C Bus Address
MCM20014 Register Address
Write
MCM20014
Ack
Bit
from
MCM20014
“
0
”
“
1
”
“
1
”
LSB
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