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參數資料
| 型號： | MCM56824AZP35R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 8K x 24 Bit Fast Static RAM |
| 中文描述： | 8K X 24 APPLICATION SPECIFIC SRAM, 35 ns, PBGA86 |
| 封裝： | PLASTIC, BGA-86 |
| 文件頁數： | 4/10頁 |
| 文件大小： | 147K |
| 代理商： | MCM56824AZP35R2 |
MCM56824A
4
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC = 5.0 V
±
10%, TA = 0 to + 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . .
0 to 3.0 V
3 ns
Output Timing Reference Level
Output Load
. . . . . . . . . . . . .
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 1a Unless Otherwise Noted
READ CYCLE TIMING
(See Notes 1, 2, and 3)
MCM56824A–20
MCM56824A–25
MCM56824A–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Read Cycle Time
tAVAV
tAVQV
tVSVQV
tE1LQV
tE2HQV
tGLQV
tE1LQX
tE2HQX
tGLQX
tAXQX
tVSXQX
tE1HQZ
tE2LQZ
tGHQZ
20
—
25
—
35
—
ns
Address Access Time
—
20
—
25
—
35
ns
MUX Control Valid to Output Valid
—
20
—
25
—
35
ns
Chip Enable to Output Valid
—
20
—
25
—
35
ns
4
Output Enable to Output Valid
—
8
—
10
—
15
ns
Output Active from Chip Enable
2
—
2
—
0
—
ns
4, 5
Output Active from Output Enable
0
—
0
—
0
—
ns
5
Output Hold from Address Change
4
—
5
—
5
—
ns
Output Hold from MUX Control Change
4
—
5
—
5
—
ns
Chip Enable to Output High–Z
0
10
0
15
0
15
ns
4, 5
Output Enable High to Output High–Z
0
8
0
15
0
15
ns
5
NOTES:
1. A read cycle is defined by W high.
2. All read cycle timings are referenced from the last valid address or vector/scalar transition to the first address or vector/scalar transition.
3. Addresses valid prior to or coincident with E1 going low or E2 going high.
4. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
5. Transition is measured
±
500 mV from steady–state voltage with load of Figure 1b. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tE1HQZ max is less than tE1LQX min, tE2LQZ max is less than tE2HQX min, and tGHQZ max is less than
tGLQX min for a given device and from device to device.
READ CYCLE
tAVQV
HIGH–Z
HIGH–Z
Q (DATA OUT)
G (OUTPUT ENABLE)
E1 (CHIP ENABLE)
V/S (MUX CONTROL)
A (ADDRESS)
tVSXQX
tGHQZ
tE1HQZ
DATA VALID
tE1LQX
tE1LQV
tGLQV
tVSVQV
tAVAV
tAXQX
tGLQX
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