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參數資料
| 型號： | MCM56824AZP35R2 |
| 廠商： | MOTOROLA INC |
| 元件分類： | DRAM |
| 英文描述： | 8K x 24 Bit Fast Static RAM |
| 中文描述： | 8K X 24 APPLICATION SPECIFIC SRAM, 35 ns, PBGA86 |
| 封裝： | PLASTIC, BGA-86 |
| 文件頁數： | 6/10頁 |
| 文件大小： | 147K |
| 代理商： | MCM56824AZP35R2 |
MCM56824A
6
MOTOROLA FAST SRAM
WRITE CYCLE TIMING
(Chip Enable Initiated, See Note 1)
MCM56824A–20
MCM56824A–25
MCM56824A–35
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Write Cycle Time
tAVAV
20
—
25
—
35
—
ns
Address Setup Time
tAVE1L
tAVE2H
0
—
0
—
0
—
ns
2
MUX Control Setup Time
tVSVE1L
tVSVE2H
0
—
0
—
0
—
ns
2
Address Valid to End of Write
tAVE1H
tAVE2L
15
—
20
—
30
—
ns
2
MUX Control Valid to End of Write
tVSVE1H
tVSVE2L
15
—
20
—
30
—
ns
2
Chip Enable to End of Write
tE1LE1H
tE2HE2L
12
—
15
—
20
—
ns
2, 3
Data Valid to End of Write
tDVE1H
tDVE2L
8
—
10
—
15
—
ns
2
Data Hold Time
tE1HDX
tE2LDX
0
—
0
—
0
—
ns
2, 4
Write Recovery Time
tE1HAX
tE2LAX
0
—
0
—
0
—
ns
2
MUX Control Recovery Time
tE1HVSX
tE2LVSX
0
—
0
—
0
—
ns
2
NOTES:
1. A write cycle starts at the latest transition of E1 low, W low, or E2 high. A write cycle ends at the earliest transition of E1 high, W high, or E2
low.
2. E1 in the timing diagrams represents both E1 and E2 with E1 asserted low and E2 asserted high.
3. If W goes low coincident with or prior to E1 low or E2 high the outputs will remain in a high–impedance state.
4. During this time the output pins may be in the output state. Signals of opposite phase must not be applied to the outputs at this time.
E1 OR E2 INITIATED WRITE CYCLE
D (DATA IN)
W (WRITE ENABLE)
E1 (CHIP ENABLE)
V/S (MUX CONTROL)
Q (DATA OUT)
A (ADDRESS)
tAVAV
tAVE1H
tE1HAX
tVSVE1H
tE1HVSX
tE1LE1H
tVSVE1L
tDVE1H
tE1HDX
DATA VALID
HIGH–Z
tAVE1L
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