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參數(shù)資料
| 型號： | MCM62110 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker |
| 中文描述： | 32K的× 9位同步雙I / O或具有奇偶校驗(yàn)檢查分離I / O快速靜態(tài)存儲器 |
| 文件頁數(shù)： | 9/12頁 |
| 文件大小： | 206K |
| 代理商： | MCM62110 |
MCM62110
9
MOTOROLA FAST SRAM
STREAM CYCLE
(See Note 1)
MCM62110–15
MCM62110–17
MCM62110–20
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Unit
Notes
Stream Cycle Time
tKHKH
15
—
17
—
20
—
ns
1, 2
Clock Low Pulse Width
tKLKH
5
—
5
—
5
—
ns
Clock High Pulse Width
tKHKL
7
—
7
—
7
—
ns
Stream Access Time
tKHQV
—
7
—
7.5
—
8
ns
Setup Times:
A
W
E1, E2
PIE
SIE
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
tAVKL
tWHKH
tEVKL
tPIEVKH
tSIEVKH
tDVKH
2.5
—
2.5
—
2.5
—
ns
Hold Times:
A
W
E1, E2
PIE
SIE
SDQ0 – SDQ7, SDQP, PDQ0 – PDQ7, PDQP
tKLAX
tKHWX
tKLEX
tKHPIEX
tKHSIEX
tKHDX
2
—
2
—
2
—
ns
Output Enable High to Q High–Z
tPOEHQZ
tSOEHQZ
0
8
0
9
0
9
ns
3
Output Enable Low to Q Active
tPOELQX
tSOELQX
0
—
0
—
0
—
ns
3
Output Enable Low to Output Valid
tPOELQV
tSOELQV
—
5
—
6
—
8
ns
NOTES:
1. A stream cycle is defined as a cycle where data is passed from one data bus to the other data bus.
2. All stream cycle timing is referenced from K.
3. Transition is measured
±
500 mV from steady–state voltage with output load of Figure 1B. This parameter is sampled and not 100% tested.
At any given voltage and temperature, tPOEHQZ is less than tPOELQX, tSOEHQZ is less than tSOELQX, and tKHQZ is less than tKHQX
for a given device.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| MCM62110FN15 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker |
| MCM62110FN17 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker |
| MCM62110FN20 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:32K x 9 Bit Synchronous Dual I/O or Separate I/O Fast Static RAM with Parity Checker |
| MCM6223YJ15 | 制造商:Motorola Inc 功能描述: |
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