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參數資料
| 型號： | MCM6343YJ15R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | 256K x 15 Bit 3.3 V Asynchronous Fast Static RAM |
| 中文描述： | 256K X 16 STANDARD SRAM, 15 ns, PDSO44 |
| 封裝： | 0.400 INCH, SOJ-44 |
| 文件頁數： | 8/10頁 |
| 文件大小： | 169K |
| 代理商： | MCM6343YJ15R |
MCM6343
8
MOTOROLA FAST SRAM
WRITE CYCLE 3
(E Controlled; See Notes 1, 2, and 3)
Parameter
Symbol
b l
MCM6343–12
MCM6343–15
U i
Unit
Notes
Min
Max
Min
Max
Write Cycle Time
tAVAV
tAVBL
tAVBH
tAVBH
tBLWH
tBLEH
12
—
15
—
ns
4
Address Setup Time
0
—
0
—
ns
Address Valid to End of Write
10
—
12
—
ns
Address Valid to End of Write (G High)
9
—
10
—
ns
Byte Pulse Width
10
—
12
—
ns
Byte Pulse Width (G High)
tBLWH
tBLEH
9
—
10
—
ns
Data Valid to End of Write
tDVBH
tBHDX
6
—
7
—
ns
Data Hold Time
0
—
0
—
ns
NOTES:
1. A write occurs during the overlap of E low and W low.
2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus
contention conditions during read and write cycles.
3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state.
4. All write cycle timings are referenced from the last valid address to the first transitioning address.
DATA VALID
tDVBH
tAVBL
tAVBH
tAVAV
tBLWH
tBHDX
HIGH–Z
HIGH–Z
A (ADDRESS)
W (WRITE ENABLE)
E (CHIP ENABLE)
Q (DATA OUT)
D (DATA IN)
tBLEH
LB, UB (BYTE ENABLE)
WRITE CYCLE 3
(E Controlled; See Notes 1, 2, and 3)
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