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參數資料
| 型號： | MCM63L918A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 9MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| 中文描述： | 9MBit快速同步后寫入靜態存儲器（800萬位同步遲寫快速靜態內存） |
| 文件頁數： | 7/20頁 |
| 文件大小： | 412K |
| 代理商： | MCM63L918A |
MCM63L836A
MCM63L918A
7
MOTOROLA FAST SRAM
DC OUTPUT BUFFER CHARACTERISTICS — PROGRAMMABLE IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(3.0 V
≤
VDD
≤
3.6 V, 0
°
C
≤
TA
≤
70
°
C, ZQ = IZQ (out) (RQ)) (See Notes 1 and 2)
Parameter
Symbol
Min
Max
Unit
Notes
Output Logic Low
IOL
(VDDQ/2) /
[(RQ/5) + 10%]
(VDDQ/2) /
[(RQ/5) – 10%]
A
3
Output Logic High
IOH
(VDDQ/2) /
[(RQ/5) + 10%]
(VDDQ/2) /
[(RQ/5) – 10%]
A
4
Light Load Output Logic Low
VOL
VOH
ZQ
VSS
0.4
V
5
Light Load Output Logic High
VDDQ – 0.4
[(RQ/5) – 10%]
VDDQ
V
6
Programmable Impedance
[(RQ/5) + 10%]
7
NOTES:
1. The impedance controlled mode is expected to be used in point–to–point applications, driving high–impedance inputs.
2. The ZQ pin is connected through RQ to VSS for the controlled impedance mode.
3. VOL = VDDQ/2.
4. VOH = VDDQ/2.
5. IOL
≤
100
μ
A.
6. | IOH |
≤
100
μ
A.
7. 175
≤
RQ
≤
375.
DC OUTPUT BUFFER CHARACTERISTICS — MINIMUM IMPEDANCE PUSH–PULL OUTPUT BUFFER MODE
(3.0 V
≤
VDD
≤
3.6 V, 0
°
C
≤
TA
≤
70
°
C)
(See Notes 1 and 2)
Parameter
Symbol
Min
Max
Unit
Notes
Output Logic Low
VOL2
VOH2
VOL3
VOH3
VSS
0.4
V
3
Output Logic High
VDDQ – 0.4
VSS
VDDQ – 0.2
VDDQ
0.2
V
4
Light Load Output Logic Low
V
5
Light Load Output Logic High
VDDQ
V
6
NOTES:
1. The push–pull output mode is expected to be used in bussed applications and may be series or parallel terminated. Conforms to the JEDEC
Standard JESD8–6 Class I.
2. The ZQ pin is connected to a 100
resistor to VSS to enable the minimum impedance mode.
3. IOL
≥
8 mA.
4. | IOH |
≥
8 mA.
5. IOL
≤
100
μ
A.
6. | IOH |
≤
100
μ
A.
CAPACITANCE
(f = 1.0 MHz, dV = 30 mV, 3.0 V
≤
VDD
≤
3.6 V, 0
°
C
≤
TA
≤
70
°
C, Periodically Sampled Rather Than 100% Tested)
Characteristic
Symbol
Typ
Max
Unit
Input Capacitance
Cin
CI/O
CCK
3.2
5
pF
Input/Output Capacitance
3.8
6
pF
CK, CK Capacitance
3.7
5
pF
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