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參數資料
| 型號： | MCM63L918A |
| 廠商： | Motorola, Inc. |
| 英文描述： | 9MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| 中文描述： | 9MBit快速同步后寫入靜態存儲器（800萬位同步遲寫快速靜態內存） |
| 文件頁數： | 8/20頁 |
| 文件大?。?/td> | 412K |
| 代理商： | MCM63L918A |
MCM63L836A
MCM63L918A
8
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(0
°
C
≤
TA
≤
70
°
C, Unless Otherwise Noted)
Input Pulse Levels
Input Rise/Fall Time
Input Timing Measurement Reference Level
Output Timing Reference Level
0.25 to 1.25 V
1 V/ns (20% to 80%)
. . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . .
0.75 V
0.75 V
. . . . . . . . . . . . . . . . . . . . . . . . .
Clock Input Timing Reference Level
ZQ for 50
Impedance
R
θ
JA Device
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Differential Cross–Point
. . . . . .
250
27
°
C/W
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING
Parameter
Symbol
b l
63L836A–3.8
63L918A–3.8
63L836A–4.0
63L918A–4.0
63L836A–4.2
63L918A–4.2
63L836A–4.5
63L918A–4.5
63L836A–5.0
63L918A–5.0
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tKLQV
tKLQX
tKLQX1
tKHQZ
3.8
—
4.0
—
4.2
—
4.5
—
5.0
—
ns
Clock High Pulse Width
1.5
—
1.6
—
1.6
—
1.6
—
2.0
—
ns
Clock Low Pulse Width
1.5
—
1.6
—
1.6
—
1.6
—
2.0
—
ns
Clock High to Output Valid
—
3.8
—
4.0
—
4.2
—
4.5
—
5.0
ns
Clock Low to Output Valid
—
1.7
—
1.8
—
1.9
—
2.0
—
2.2
ns
Clock Low to Output Hold
0.7
—
0.7
—
0.7
—
0.7
—
0.7
—
ns
1
Clock Low to Output Low–Z
0.7
—
0.7
—
0.7
—
0.7
—
0.7
—
ns
1, 2
Clock High to Output
High–Z
0.7
1.7
0.7
1.8
0.7
1.9
0.7
2.0
0.7
2.2
ns
1, 2
ZZ High to Sleep Mode
tZZE
tZZR
tAVKH
tDVKH
tSVKH
tWVKH
tKHAX
tKHDX
tKHSX
tKHWX
3.0
—
3.0
—
3.0
—
3.0
—
3.0
—
ns
ZZ Low to Recovery
—
10.0
—
10.0
—
10.0
—
10.0
—
10.0
ns
Setup Times:
Address
Data In
Chip Select
Write Enable
0.4
—
0.4
—
0.4
—
0.4
—
0.4
—
ns
Hold Times:
Address
Data In
Chip Select
Write Enable
0.8
—
0.8
—
0.8
—
0.8
—
0.8
—
ns
NOTES:
1. This parameter is sampled and not 100% tested.
2. Measured at
±
200 mV from steady state.
The table of timing values shows either a mini-
mum or a maximum limit for each parameter. Input
requirements are specified from the external system
point of view. Thus, address setup time is shown as
a minimum since the system must supply at least
that much time. On the other hand, responses from
the memory are specified from the device point of
view. Thus, the access time is shown as a maximum
since the device never provides data later than that
time.
TIMING LIMITS
DEVICE
UNDER
TEST
ZQ
50
50
0.75 V
VDDQ/2
Vref
250
Figure 1. AC Test Load
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