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參數(shù)資料
| 型號(hào)： | MCM63P531TQ7 |
| 廠商： | MOTOROLA INC |
| 元件分類(lèi)： | DRAM |
| 英文描述： | Replaced by PTH12000W : |
| 中文描述： | 32K X 32 CACHE SRAM, 7 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 24/27頁(yè) |
| 文件大小： | 328K |
| 代理商： | MCM63P531TQ7 |
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MCM63P636
24
MOTOROLA FAST SRAM
STANDARD AND DEVICE SPECIFIC (PUBLIC) INSTRUCTION CODES
Instruction
Code*
Description
IDCODE
001**
Preloads ID register and places it between TDI and TDO. Does not affect RAM operation.
HIGH–Z
010
Captures I/O ring contents. Places the bypass register between TDI and TDO. Forces all DQ pins
to High–Z.
NOT IEEE 1149.1 COMPLIANT.
BYPASS
011
Places bypass register between TDI and TDO. Does not affect RAM operation.
NOT IEEE 1149.1
COMPLIANT.
SAMPLE/PRELOAD
100
Captures I/O ring contents. Places the boundary scan register between TDI and TDO. Does not
affect RAM operation.
Does not implement IEEE 1149.1 Preload function.
NOT IEEE 1149.1 COMPLIANT.
*Instruction codes expressed in binary, MSB on left, LSB on right.
**Default instruction automatically loaded when TRST asserted or in test–logic–reset state.
STANDARD (PRIVATE) INSTRUCTION CODES
Instruction
Code*
Description
NO OP
000
Do not use these instructions; they are reserved for future use.
NO OP
101
Do not use these instructions; they are reserved for future use.
NO OP
110
Do not use these instructions; they are reserved for future use.
NO OP
111
Do not use these instructions; they are reserved for future use.
* Instruction codes expressed in binary, MSB on left, LSB on right.
CAPTURE–DR
EXIT1–DR
EXIT2–DR
UPDATE–DR
CAPTURE–IR
EXIT1–IR
EXIT2–IR
UPDATE–IR
SHIFT–IR
PAUSE–IR
SHIFT–DR
PAUSE–DR
TEST–LOGIC
RESET
RUN–TEST/
IDLE
SELECT
DR–SCAN
SELECT
IR–SCAN
1
0
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
0
Figure 10. TAP Controller State Diagram
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PDF描述 |
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| MCM63P531TQ8 | 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P531TQ9 | 32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P631 | 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P631TQ7 | 64K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MCM63P531TQ7R | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P531TQ8 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P531TQ8R | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P531TQ9 | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P531TQ9R | 制造商:MOTOROLA 制造商全稱(chēng):Motorola, Inc 功能描述:32K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
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