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參數資料
| 型號： | MCM63P733ATQ100R |
| 廠商： | MOTOROLA INC |
| 元件分類： | SRAM |
| 英文描述： | ER 7C 7#16S SKT RECP |
| 中文描述： | 128K X 32 CACHE SRAM, 4.5 ns, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數： | 9/16頁 |
| 文件大小： | 238K |
| 代理商： | MCM63P733ATQ100R |
MCM63P733A
9
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VDD = 3.3 V + 10%, – 5%, TA = 0 to 70
°
C, Unless Otherwise Noted)
Input Timing Measurement Reference Level
Input Pulse Levels
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
. . . . . . . . . . . . . . . . . . . . . .
1.25 V
0 to 2.5 V
. . . . . . . . . . . . . .
1.0 V/ns (20 to 80%)
Output Timing Reference Level
Output Load
. . . . . . . . . . . . . .
1.25 V
. . . . . . . . . . . . . . . . . . . . . . . . .
See Figure 2 Unless Otherwise Noted
READ/WRITE CYCLE TIMING
(See Notes 1 through 4)
Parameter
Symbol
b l
63P733A–133
133 MHz
63P733A–117
117 MHz
63P733A–100
100 MHz
63P733A–90
90 MHz
U i
Unit
Notes
Min
Max
Min
Max
Min
Max
Min
Max
Cycle Time
tKHKH
tKHKL
tKLKH
tKHQV
tGLQV
7.5
—
8.5
—
10
—
11
—
ns
Clock High Pulse Width
3
—
3.4
—
4
—
4.4
—
ns
Clock Low Pulse Width
3
—
3.4
—
4
—
4.4
—
ns
Clock Access Time
—
4
—
4.2
—
4.5
—
5
ns
Output Enable to Output
Valid
—
3.8
—
3.8
—
4.5
—
5
ns
Clock High to Output
Active
tKHQX1
0
—
0
—
0
—
0
—
ns
5, 6
Clock High to Output
Change
tKHQX2
1.5
—
1.5
—
1.5
—
1.5
—
ns
6
Output Enable to Output
Active
tGLQX
0
—
0
—
0
—
0
—
ns
5, 6
Output Disable to Q
High–Z
tGHQZ
—
3.8
—
3.8
—
4.5
—
5
ns
5, 6
Clock High to Q High–Z
tKHQZ
tADKH
tADSKH
tDVKH
tWVKH
tEVKH
1.5
7.5
1.5
8.5
1.5
10
1.5
11
ns
5, 6
Setup Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
2
—
2
—
2
—
2
—
ns
Hold Times:
Address
ADSP, ADSC, ADV
Data In
Write
Chip Enable
tKHAX
tKHADSX
tKHDX
tKHWX
tKHEX
0.5
—
0.5
—
0.5
—
0.5
—
ns
Sleep Mode Standby
tZZS
—
2 x
tKHKH
—
2 x
tKHKH
—
2 x
tKHKH
—
2 x
tKHKH
ns
Sleep Mode Recovery
tZZREC
2 x
tKHKH
—
2 x
tKHKH
—
2 x
tKHKH
—
2 x
tKHKH
—
ns
Sleep Mode High to Q
High–Z
tZZQZ
—
15
—
15
—
15
—
15
ns
NOTES:
1. Write is defined as either any SBx and SW low or SGW is low. Chip Enable is defined as SE1 low, SE2 high, and SE3 low whenever ADSP
or ADSC is asserted.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care after write cycle begins. To prevent bus contention, G should be negated prior to start of write cycle.
4. In order to reduce test correlation issues and to reduce the effects of application specific input edge rate variations on correlation between
data sheet parameters and actual system performance, FSRAM AC parametric specifications are always specified at VDDQ/2. In some
design exercises, it is desirable to evaluate timing using other reference levels. Since the maximum test input edge rate is known and is given
in the AC Test Conditions section of the data sheet as 1 V/ns, one can easily interpolate timing values to other reference levels.
5. This parameter is sampled and not 100% tested.
6. Measured at
±
200 mV from steady state.
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相關代理商/技術參數 |
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| MCM63P733ATQ117 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P733ATQ117R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P733ATQ133 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P733ATQ133R | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
| MCM63P733ATQ90 | 制造商:MOTOROLA 制造商全稱:Motorola, Inc 功能描述:128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM |
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