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參數資料
| 型號： | MCM63R736 |
| 廠商： | Motorola, Inc. |
| 英文描述： | 4MBit Synchronous Late Write Fast Static RAM(4M位同步遲寫快速靜態RAM) |
| 中文描述： | 晚寫的4Mb同步快速靜態存儲器（4分位同步遲寫快速靜態內存） |
| 文件頁數： | 1/21頁 |
| 文件大?。?/td> | 311K |
| 代理商： | MCM63R736 |
MCM63R736
MCM63R818
1
Motorola, Inc. 1999
4M Late Write HSTL
The MCM63R736/818 is a 4M–bit synchronous late write fast static RAM
designed to provide high performance in secondary cache and ATM switch,
Telecom, and other high speed memory applications. The MCM63R818
(organized as 256K words by 18 bits), and the MCM63R736 (organized as 128K
words by 36 bits) are fabricated in Motorola’s high performance silicon gate
copper CMOS technology.
The differential clock (CK) inputs control the timing of read/write operations of
the RAM. At the rising edge of CK, all addresses, write enables, and synchronous
selects are registered. An internal buffer and special logic enable the memory to
accept write data on the rising edge of CK, a cycle after address and control sig-
nals. Read data is also driven on the rising edge of CK.
The RAM uses HSTL inputs and outputs. The adjustable input trip–point (Vref)
and output voltage (VDDQ) gives the system designer greater flexibility in
optimizing system performance.
The synchronous write and byte enables allow writing to individual bytes or the
entire word.
The impedance of the output buffers is programmable, allowing the outputs to
match the impedance of the circuit traces which reduces signal reflections.
Byte Write Control
2.5 V –5% to 3.3 V +10% Operation
2.375 V to 3.6 V Operation
HSTL — I/O (JEDEC Standard JESD8–6 Class I Compatible)
HSTL — User Selectable Input Trip–Point
HSTL — Compatible Programmable Impedance Output Drivers
Register to Register Synchronous Operation
Boundary Scan (JTAG) IEEE 1149.1 Compatible
Differential Clock Inputs
Optional x18 or x36 Organization
MCM63R736/818–3 = 3 ns
MCM63R736/818–3.3 = 3.3 ns
MCM63R736/818–3.7 = 3.7 ns
MCM63R736/818–4 = 4 ns
MCM63R736/818–4.4 = 4.4 ns
MCM63R736/818–5 = 5 ns
Sleep Mode Operation (ZZ pin)
119–Bump, 50 mil (1.27 mm) Pitch, 14mm x 22mm Flipped Chip Plastic
Ball Grid Array (PBGA) Package
Order this document
by MCM63R736/D
SEMICONDUCTOR TECHNICAL DATA
MCM63R736
MCM63R818
FC PACKAGE
FLIPPED CHIP PBGA
CASE 999E–01
8/6/99
相關PDF資料 |
PDF描述 |
|---|---|
| MCM63R819 | 4MBit Synchronous Late Write Fast Static RAM(4M位同步遲寫快速靜態RAM) |
| MCM63R836 | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| MCM63R918 | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| MCM63R918A | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
| MCM63R836A | 8MBit Synchronous Late Write Fast Static RAM(8M位同步遲寫快速靜態RAM) |
相關代理商/技術參數 |
參數描述 |
|---|---|
| MCM63R836 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R836A | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:8M Late Write HSTL |
| MCM63R836FC3.0 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R836FC3.0R | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
| MCM63R836FC3.3 | 制造商:FREESCALE 制造商全稱:Freescale Semiconductor, Inc 功能描述:MCM63R836 |
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